Lara Williams
lara.williams@embeddedroad.example
FPGA Verification Engineer
Builds verification environments and timing-clean FPGA datapaths for signal-processing products.
📍 Cambridge, UK
Level 10
Embedded Developer · 9,764 XP
Top 6.8% globally
116
Topics Learned
0
Rare Skills
31d
Current Streak
39d
Longest Streak
Evidence
- 116 across 4 branchesTopics learnedFrom progress
- Band-to-Band Tunneling in Ultra-Thin Devices · VLSI & Chip Design · 2026-09-12
- ASCII, Unicode, and Character Encoding Standards · Digital Electronics · 2026-09-11
- Aliasing: Overlapping Spectra When fs < 2·fmax · Signal Processing · 2026-09-10
- Absolute Error and Relative Error (%) Calculation · Instrumentation & Measurement · 2026-09-09
- Body Bias (FBB, RBB) for Power-Performance · VLSI & Chip Design · 2026-09-08
- Arithmetic Shifts vs. Logical Shifts · Digital Electronics · 2026-09-07
- 116Active daysFrom progress
- Current streak: 31 days
- Longest streak: 39 days
- 1 (1 with source)ProjectsSelf-reported
- SystemVerilog Reference Design · github
Verified claims were checked by a person or cannot be produced without doing the work. Derived claims are computed from this profile’s own progress records. Self-reported claims were entered by the engineer and have not been checked.
Career Achievements
⭐
High Voltage
🌐
Full Stack Breadth
Rare
🌊
Deep Current
📘
Foundational ×100
Rare
🌊
Signal Processing Curious
Common
🌊
Signal Processing Curious
Common
🌊
Signal Processing Explorer
Common
🌊
Signal Processing Explorer
Common
🌊
Signal Processing Tinkerer
Common
🌊
Signal Processing Tinkerer
Common
🌊
Signal Processing Tinkerer
Common
🌊
Signal Processing Learner
Common
Engineering Projects
SystemVerilog Reference Design
FPGA Verification Engineer
Lara Williams built a production-oriented project around SystemVerilog, UVM, Timing closure.
SystemVerilogUVMTiming closureAXISystemVerilogUVM
Branches
Instrumentation & Measurement9%
Digital Electronics7%
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