Priya Nair

priya.nair@sci-hw.example

ASIC Design Engineer

Owns RTL blocks from microarchitecture through verification closure and low-power implementation.

📍 Bengaluru, India

Level 9
Junior Engineer · 9,100 XP
Top 13.6% globally
121
Topics Learned
29
Rare Skills
35d
Current Streak
43d
Longest Streak

Engineering Projects

RTL Reference Design
ASIC Design Engineer

Priya Nair built a production-oriented project around RTL, CDC, Synthesis.

RTLCDCSynthesisLow power designRTLCDC
Repo

Branches

Digital Electronics30%

ATS-optimized CV available

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