Priya Nair
priya.nair@embeddedroad.example
ASIC Design Engineer
Owns RTL blocks from microarchitecture through verification closure and low-power implementation.
📍 Bengaluru, India
Level 9
Junior Engineer · 8,815 XP
Top 5.4% globally
121
Topics Learned
0
Rare Skills
35d
Current Streak
43d
Longest Streak
Evidence
- 121 across 3 branchesTopics learnedFrom progress
- 3D NAND: Vertical Channel, Staircase Contact, Layer Count · VLSI & Semiconductor · 2026-09-12
- 2D Materials: Graphene, MoS2, WSe2 for FET Applications · VLSI & Semiconductor · 2026-09-12
- ASCII, Unicode, and Character Encoding Standards · Digital Electronics · 2026-09-11
- Band-to-Band Tunneling in Ultra-Thin Devices · VLSI & Chip Design · 2026-09-10
- Avalanche Breakdown: Impact Ionization Coefficient · VLSI & Semiconductor · 2026-09-09
- Arithmetic Shifts vs. Logical Shifts · Digital Electronics · 2026-09-08
- 120Active daysFrom progress
- Current streak: 35 days
- Longest streak: 43 days
- 1 (1 with source)ProjectsSelf-reported
- RTL Reference Design · github
Verified claims were checked by a person or cannot be produced without doing the work. Derived claims are computed from this profile’s own progress records. Self-reported claims were entered by the engineer and have not been checked.
Career Achievements
🌐
Full Stack Breadth
Rare
🌊
Deep Current
📘
Foundational ×100
Rare
🔬
VLSI & Curious
Common
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VLSI & Curious
Common
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VLSI & Explorer
Common
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VLSI & Explorer
Common
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VLSI & Tinkerer
Common
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VLSI & Tinkerer
Common
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VLSI & Tinkerer
Common
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VLSI & Learner
Common
🔬
VLSI & Learner
Common
Engineering Projects
RTL Reference Design
ASIC Design Engineer
Priya Nair built a production-oriented project around RTL, CDC, Synthesis.
RTLCDCSynthesisLow power designRTLCDC
Branches
Digital Electronics10%
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