Depletion Region: Width, Electric Field, Space Charge

Every p-n junction — whether it's a rectifier diode, a BJT's base-emitter junction, or a MOSFET's body diode — hides a region a few tenths of a micron wide that determines its breakdown voltage, its junction capacitance, and how fast it can switch. That region is the depletion region, and quantifying its width, field, and charge is the first real calculation every semiconductor device model builds on.

Why a Depletion Region Forms

When p-type and n-type material are joined, the large carrier concentration gradient drives diffusion: electrons from the n-side diffuse into the p-side and holes from the p-side diffuse into the n-side. Each diffusing carrier leaves behind a fixed, ionized dopant atom — a donor ion (positive) on the n-side, an acceptor ion (negative) on the p-side. These ions can't move; they're locked in the crystal lattice.

The result is a narrow region straddling the junction that has been stripped of mobile carriers, exposing the net fixed charge of the ionized dopants. This is the space charge region, commonly called the depletion region because it's depleted of free carriers. The exposed charge sets up an electric field that opposes further diffusion — equilibrium is reached when drift current (driven by this field) exactly cancels diffusion current, giving zero net current with no external bias, as required.

Space Charge Density

Under the depletion approximation (the standard idealization used in nearly all hand analysis), the region is divided sharply into two zones:

• n-side depletion width x_n: fully ionized donors, charge density ρ = +q·N_D
• p-side depletion width x_p: fully ionized acceptors, charge density ρ = −q·N_A

Outside these widths, the material is assumed perfectly neutral (no field, no net charge) — an abrupt boundary rather than a gradual taper. This is an approximation, but it matches full numerical solutions closely except very near the edges.

Charge neutrality requires the total ionized charge on each side to balance:

q·N_D·x_n = q·N_A·x_p   →   N_D·x_n = N_A·x_p

This immediately tells you the depletion region extends further into the more lightly doped side. In a typical diode with N_A ≫ N_D (or vice versa), the depletion region is almost entirely on the lightly doped side — the basis for the "one-sided junction" approximation used in most device work.

Electric Field Profile

Applying Gauss's law (dE/dx = ρ/ε) to the linear charge density on each side gives a triangular field profile: E rises linearly from zero at the n-side edge to a peak at the metallurgical junction (x = 0), then falls linearly back to zero at the p-side edge.

n-side (−x_n < x < 0):  E(x) = −(q·N_D/ε_s)·(x + x_n)
p-side (0 < x < x_p):   E(x) =  (q·N_A/ε_s)·(x − x_p)

Peak field at the junction (x = 0):

E_peak = q·N_D·x_n/ε_s = q·N_A·x_p/ε_s

where ε_s is the semiconductor permittivity (≈1.04×10⁻¹⁰ F/m for silicon). The field points from n to p (from positive donor ions to negative acceptor ions), reinforcing why it opposes hole and electron diffusion across the junction. This peak field is what determines avalanche breakdown — silicon breaks down near E_crit ≈ 3×10⁵ V/cm (roughly, doping-dependent), so peak field is a first-order breakdown-voltage predictor.

Built-In Potential and Total Width

Integrating −E(x) across the depletion region gives the built-in potential V_bi, the barrier that stops diffusion at equilibrium:

V_bi = (kT/q)·ln(N_A·N_D/ni²)

At room temperature (kT/q ≈ 0.0259 V) and with silicon's ni ≈ 1×10¹⁰ cm⁻³, typical junctions give V_bi ≈ 0.6–0.7 V.

The total depletion width under an applied reverse bias V_R (with V_R defined positive for reverse bias, so the effective barrier becomes V_bi + V_R) is:

W = x_n + x_p = √[ (2·ε_s/q) · (1/N_A + 1/N_D) · (V_bi + V_R) ]

Key scaling behaviors:

• W ∝ √(V_bi + V_R) — width grows with the square root of reverse bias, not linearly. This is why junction capacitance (∝ 1/W) drops off gradually rather than sharply as reverse bias increases.
• W ∝ 1/√N (for the dominant, lightly-doped side) — heavier doping compresses the depletion region and raises the peak field for the same voltage, which is why heavily doped junctions break down at lower voltages.

Worked Example

Silicon p-n junction, N_A = 1×10¹⁸ cm⁻³, N_D = 1×10¹⁶ cm⁻³, T = 300 K, no external bias (V_R = 0).

Step 1 — Built-in potential:

V_bi = 0.0259 · ln[(1e18 · 1e16)/(1e10)²]
     = 0.0259 · ln(1e34/1e20)
     = 0.0259 · ln(1e14)
     = 0.0259 · 32.24 ≈ 0.835 V

Step 2 — Total width (ε_s = 1.04×10⁻¹⁰ F/m, q = 1.6×10⁻¹⁹ C; convert N to m⁻³: N_A = 1×10²⁴ m⁻³, N_D = 1×10²² m⁻³):

1/N_A + 1/N_D ≈ 1/1e22 = 1.0×10⁻²² m³   (N_A term negligible — one-sided junction)

W = √[ (2·1.04e-10/1.6e-19) · 1.0e-22 · 0.835 ]
  = √[ (1.3e9) · 1.0e-22 · 0.835 ]
  = √[1.086e-13]
  ≈ 3.30×10⁻⁷ m ≈ 0.33 µm

Step 3 — Split between sides (N_D·x_n = N_A·x_p, and since N_A ≫ N_D, essentially all of W sits on the n-side):

x_n ≈ W = 0.33 µm,   x_p ≈ x_n·(N_D/N_A) = 0.33 µm × 1e-2 ≈ 3.3 nm

Step 4 — Peak field check:

E_peak = q·N_D·x_n/ε_s = (1.6e-19 · 1e22 · 3.3e-7)/1.04e-10 ≈ 5.08×10⁴ V/cm... 

converting carefully: numerator = 1.6e-19 × 1e22 × 3.3e-7 = 5.28×10⁻⁴; divide by 1.04e-10 → 5.08×10⁶ V/m = 5.08×10⁴ V/cm.

Verification via V_bi = ½·E_peak·W (area under the triangular field): ½ × 5.08×10⁴ V/cm × 0.33×10⁻⁴ cm = 0.838 V — matches the 0.835 V from Step 1 within rounding, confirming internal consistency.

Design Implications

• Breakdown voltage is set by the lightly doped side's peak field reaching E_crit — lower the doping there (at the cost of higher on-resistance/series resistance) to raise breakdown voltage, a core power-device tradeoff (seen directly in power MOSFET and IGBT design).
• Junction capacitance C_j = ε_s·A/W falls as reverse bias increases (W grows), which is exploited deliberately in varactor diodes and must be accounted for in RF and high-speed switching designs.
• BJT base width modulation (Early effect) arises because the collector-base depletion region eats into the base as V_CB increases, effectively shrinking the neutral base and changing β and output resistance.
• CMOS scaling pushes depletion widths down to tens of nanometers, which is why short-channel effects (DIBL, punch-through) become significant as nodes shrink — the depletion regions from source and drain start to interact.

Key Takeaways

• The depletion region is a carrier-free zone of exposed, immobile dopant ions formed by diffusion across a p-n junction; its field balances diffusion current at equilibrium.
• Under the depletion approximation, charge is a uniform density on each side; charge neutrality requires N_D·x_n = N_A·x_p, so the region extends mainly into the lightly doped side.
• The electric field is triangular, peaking at the metallurgical junction; peak field governs avalanche breakdown.
• Total width W ∝ √(V_bi + V_R) and ∝ 1/√N — width grows sublinearly with reverse bias and shrinks with heavier doping.
• These relationships directly explain junction capacitance behavior, breakdown voltage tradeoffs, the Early effect, and short-channel effects in scaled MOSFETs.