Technical Articles

Embedded engineering blog

Articles organised by roadmap branch and topic. Reading a topic’s article is how you mark it learned.

Analog Electronics79 articles

Embedded Systems39 articles

ADC Key Specs: Resolution, ENOB, INL, DNL, SNRADC Key Specs: Resolution, ENOB, INL, DNL, SNRWhy ADC Specs Matter for Embedded Design Moving beyond bit count: what specs really tell you A "12-bit ADC" tells you almost nothing about how well it will measure your signal. Re...8 min read
Analog Comparator: Hysteresis and Wake-Up ApplicationAnalog Comparator: Hysteresis & Wake-Up DesignHow to use analog comparators with hysteresis to build ultra-low-power wake-up and threshold-detection circuits without touching the ADC or CPU.12 min read
CMSIS-NN: ARM-Optimized Kernel Library for Cortex-MCMSIS-NN: ARM-Optimized Kernel Library for Cortex-MHow ARM's CMSIS-NN library turns quantized int8 CNN layers into SIMD/DSP-instruction kernels on Cortex-M, with the math and measured speedups behind it.6 min read
Camera Interface: DVP (Digital Video Port) and MIPI CSI-2Camera Interface: DVP (Digital Video Port) and MIPI CSI-2A quantitative comparison of parallel DVP and serial MIPI CSI-2 camera interfaces — bandwidth limits, pin cost, and how to pick the right one by the numbers.7 min read
Color Space Conversion: RGB888 → RGB565 → GrayscaleColor Space Conversion: RGB888 → RGB565 → GrayscaleHow and why embedded vision pipelines downcast RGB888 to RGB565 for displays and to grayscale for CNN/CV input — with bit-packing math, fixed-point luma, and error analysis.8 min read
Continual / Incremental Learning on Embedded DevicesContinual / Incremental Learning on Embedded DevicesHow MCUs and NPUs update models in the field without catastrophic forgetting: EWC, replay, and frozen-backbone prototype learning, with a real memory budget worked example.7 min read
EThos-U55 / U65: Arm ML Processor for Cortex-M SystemsEThos-U55 / U65: Arm ML Processor for Cortex-M SystemsHow Arm's Ethos-U55/U65 microNPUs offload CNN inference from Cortex-M cores, how Vela compiles and partitions models, and how to size real throughput and power.7 min read
Edge AI Overview: Inference at the Device vs. CloudEdge AI Overview: Inference at the Device vs. CloudA quantitative comparison of on-device and cloud inference — latency budgets, power draw, model-size ceilings, and a worked wake-word power example.7 min read
Edge Impulse: Data Collection, Training, Deployment to MCUEdge Impulse: Data Collection, Training, Deployment to MCUA practical walkthrough of Edge Impulse's data-to-deployment pipeline: what to get right in data collection, where the DSP block burns cycles, and how EON affects MCU RAM budgets.8 min read
Embedded OpenCV: ARM Neon OptimizationEmbedded OpenCV: ARM Neon OptimizationHow ARM NEON accelerates OpenCV's core kernels, why real speedups land at 3–8× instead of the theoretical 16×, and how to verify NEON is actually active in your build.6 min read
Face Detection on MCU: Haar Cascade, MobileNet-SSDFace Detection on MCU: Haar Cascade, MobileNet-SSDCompares Haar cascades and quantized MobileNet-SSD for on-MCU face detection, with the compute, RAM, and latency math behind each approach in detail.7 min read
Federated Learning on MCU: Privacy-Preserving On-DeviceFederated Learning on MCU: Privacy-Preserving On-DeviceHow to fit federated learning's train-locally, share-only-updates pattern onto Cortex-M budgets: what to train, what to send, and how to bound privacy leakage.7 min read
Future Edge AI: RISC-V AI Extensions, Chiplet NPU IntegrationFuture Edge AI: RISC-V AI Extensions, Chiplet NPU IntegrationHow RISC-V vector/custom ISA extensions and chiplet-based NPU integration are replacing fixed-function edge AI accelerators, with a worked bandwidth/energy budget.7 min read
Image Preprocessing on MCU: Resize, Crop, NormalizeImage Preprocessing on MCU: Resize, Crop, NormalizeHow resize, crop, and normalize stages on an MCU must exactly mirror training-time preprocessing — and why getting the order or math wrong silently costs accuracy.7 min read
JPEG Decode on MCU: libjpeg-turbo, STM32 JPEG HW IPJPEG Decode on MCU: libjpeg-turbo, STM32 JPEG HW IPComparing software JPEG decode (libjpeg-turbo on Cortex-M DSP extensions) against STM32's hardware JPEG codec IP, with a worked frame-budget example for a real-time vision pipeline.7 min read
Keyword Spotting (KWS): DS-CNN on Cortex-M for Wake-WordKeyword Spotting (KWS): DS-CNN on Cortex-M for Wake-WordHow Depthwise-Separable CNNs deliver always-on wake-word detection on Cortex-M MCUs — architecture, MAC/memory sizing, quantization, and a real power budget.6 min read
Knowledge Distillation: Teacher-Student Model CompressionKnowledge Distillation: Teacher-Student Model CompressionHow training a small student network on a large teacher's soft outputs recovers accuracy that pruning and quantization alone cannot, with a worked keyword-spotting sizing example.6 min read
MAX78000: Ultra-Low-Power CNN AcceleratorMAX78000: Ultra-Low-Power CNN AcceleratorHow the MAX78000's weight-stationary, in-memory CNN accelerator hits sub-µJ inference — and the SRAM/quantization constraints that shape any model targeting it.6 min read
MCU AI Frameworks: TensorFlow Lite Micro (TFLite Micro)MCU AI Frameworks: TensorFlow Lite Micro (TFLite Micro)How TensorFlow Lite Micro fits neural nets into KB-scale RAM using a static tensor arena — with the allocation math worked through on a real model.6 min read
MCU Inference Benchmarks: MLPerf Tiny ResultsMCU Inference Benchmarks: MLPerf Tiny ResultsHow to read MLPerf Tiny's closed vs. open division results correctly, and why energy-delay product — not latency alone — is the metric that predicts real battery life.6 min read
Memory Optimization: Scratch Buffer, In-Place OperationsMemory Optimization: Scratch Buffer, In-Place OperationsHow to shrink an inference graph's peak RAM by reusing scratch buffers and writing operator outputs in place — the difference between fitting a model and not.7 min read
Model Deployment Pipeline: CI/CD for Edge AI ModelsModel Deployment Pipeline: CI/CD for Edge AI ModelsHow to build a CI/CD pipeline for edge AI models — data/model versioning, quantized target builds, hardware-in-the-loop gates, and staged OTA rollout.7 min read
Model Pruning: Weight Magnitude, Structured vs. UnstructuredModel Pruning: Weight Magnitude, Structured vs. UnstructuredHow to shrink a neural network for MCU deployment with weight-magnitude pruning, and why structured pruning — not unstructured — is usually what actually speeds up Cortex-M inference.8 min read
NDP120 / NDP200: Syntiant Neural Decision ProcessorNDP120 / NDP200: Syntiant Neural Decision ProcessorHow Syntiant's NDP120/NDP200 inference ASICs enable always-on keyword spotting and sensor classification at microwatt power — with a worked battery-life budget.7 min read
Neuromorphic Computing: Intel Loihi, BrainScaleS BasicsNeuromorphic Computing: Intel Loihi, BrainScaleS BasicsHow spiking neuron models turn Intel Loihi and BrainScaleS into event-driven processors, and when that architecture actually beats a dense NPU on energy.6 min read
ONNX Runtime for Embedded: Inference on Cortex-AONNX Runtime for Embedded: Inference on Cortex-AHow ONNX Runtime schedules graphs, quantizes, and picks execution providers on Cortex-A Linux boards — with a worked MobileNetV2 latency budget.7 min read
OTA Update for AI Model: Delta Model Update StrategyOTA Update for AI Model: Delta Model Update StrategyHow delta encoding of weight tensors cuts OTA payloads 10–50× versus full-model transfer, with a worked bandwidth/compression example and safe reconstruction on flash-limited MCUs.7 min read
Object Detection on MCU: YOLO-Nano, TinyYOLOObject Detection on MCU: YOLO-Nano, TinyYOLOHow TinyYOLO and YOLO-Nano compress object detection to fit Cortex-M SRAM and MAC budgets, with a worked sizing example on an STM32H7-class MCU.6 min read
OpenMV Cam: Machine Vision on STM32H7OpenMV Cam: Machine Vision on STM32H7How an STM32H7's Cortex-M7 core, DCMI DMA pipeline, and MicroPython stack turn OpenMV Cam into a real-time classical-CV and light-CNN vision platform — and where its limits are.7 min read
Operator Fusion: Reducing Memory and Compute OverheadOperator Fusion: Reducing Memory and Compute OverheadOperator fusion merges chained ops like Conv+BatchNorm+ReLU into one kernel call, cutting memory traffic and dispatch overhead — often the biggest lever on MCU inference latency.7 min read
Optical Flow on MCU: Lucas-Kanade for UAV StabilizationOptical Flow on MCU: Lucas-Kanade for UAV StabilizationHow the Lucas-Kanade optical flow algorithm reduces to a cheap 2×2 linear solve per point, and how to fit it into a Cortex-M cycle budget for UAV hover stabilization.7 min read
Person Detection: MobileNet-v2 on CMSIS-NNPerson Detection: MobileNet-v2 on CMSIS-NNHow MobileNet-v2's inverted-residual blocks and CMSIS-NN's INT8 SIMD kernels combine to run real-time, low-power person detection on a Cortex-M MCU.6 min read
Post-Training Quantization: FP32 → INT8 Weight ConversionPost-Training Quantization: FP32 → INT8 Weight ConversionHow FP32 weights become INT8 for MCU inference: the scale/zero-point math, per-channel quantization, integer requantization, and why calibration makes or breaks accuracy.6 min read
PyTorch Mobile: Lightweight Inference on Embedded LinuxPyTorch Mobile: Lightweight Inference on Embedded LinuxHow to export PyTorch models to TorchScript and run them efficiently with LibTorch on Cortex-A Linux, with quantization math and a real latency budget check.7 min read
Quantization-Aware Training (QAT): Simulated QuantizationQuantization-Aware Training (QAT): Simulated QuantizationHow simulated quantization and the straight-through estimator let a network learn weights that survive INT8 (or lower) rounding, closing the accuracy gap PTQ leaves behind.6 min read
STM32N6: Neural ART Accelerator on STM32STM32N6: Neural ART Accelerator on STM32How ST's Neural ART NPU on STM32N6 shifts CNN inference from CPU-bound compute to memory-bound pipelines — architecture, toolchain, and a worked throughput estimate.7 min read
TFLite Micro Workflow: Train → Convert → Quantize → DeployTFLite Micro Workflow: Train → Convert → Quantize → DeployA precise walkthrough of the TFLite Micro pipeline — training in float32, converting to FlatBuffer, INT8 quantization math, and sizing the deployment memory arena.7 min read
Time-Series Classification: 1D CNN on Sensor DataTime-Series Classification: 1D CNN on Sensor DataHow to size, quantize, and deploy a 1D convolutional network for classifying IMU/vibration sensor windows on Cortex-M, with full MAC and memory budgeting.7 min read
TinyML Benchmarking: eAI, TinyMLPerf, MLCommonsTinyML Benchmarking: eAI, TinyMLPerf, MLCommonsHow MLPerf Tiny, EEMBC's eAI suite, and MLCommons standardize accuracy, latency, and energy so vendor TOPS claims can actually be compared across silicon.7 min read

PCB & Hardware Design1 article

Annular Ring: IPC-6012 Minimum Ring RequirementAnnular Ring: IPC-6012 Minimum Ring RequirementA practical look at IPC-6012 annular ring minimums, the tolerance stack-ups behind them, and when high-reliability designs should exceed the spec.9 min read

Medical Device Eng.1 article

CT Hounsfield Units: Tissue Density ClassificationCT Hounsfield Units: Tissue Density ClassificationA practical breakdown of Hounsfield Units, tissue HU ranges, and the calibration factors engineers must control to keep CT reconstruction pipelines accurate.7 min read

Embedded engineering blog

Analog Electronics79 articles

Embedded Systems39 articles

PCB & Hardware Design1 article

Medical Device Eng.1 article

IoT & Connectivity40 articles

Embedded & Firmware3 articles