VLSI & Chip Design
CMOS device physics, RTL/HDL design, logic synthesis, STA, analog IC, physical design (PnR), DFT, and advanced nodes.
280 topics · 2 with articles
Intern Engineer· 1 of 40
- Band-to-Band Tunneling in Ultra-Thin DevicesArticle coming
- Body Bias (FBB, RBB) for Power-PerformanceArticle coming
- CMOS Dynamic Power: Switching, Short-CircuitArticle coming
- CMOS Inverter: Static Transfer CharacteristicArticle coming
- CMOS NAND / NOR Gate SizingArticle coming
- CMOS Static Power: Subthreshold, Gate, GIDLArticle coming
- Channel Length Modulation LambdaArticle coming
- Contact and Via Resistance ModelingArticle coming
- Device Characterization: Id-Vgs, Id-Vds CurvesArticle coming
- Dopant Profiling: SIMS MeasurementArticle coming
- ESD Structures: Diode, GGNMOS, SCRArticle coming
- Electromigration: Blacks EquationArticle coming
- FinFET Device Physics vs. Planar MOSFETArticle coming
- Gate Oxide Reliability: TDDB and SILCArticle coming
- Gate-All-Around (GAA) Nanosheet PhysicsArticle coming
- High-k / Metal Gate Stack (HKMG)Article coming
- Hot Carrier Injection (HCI) MechanismArticle coming
- Interconnect RC Delay: Elmore ModelArticle coming
- Latch-Up Mechanism and Guard Ring DesignArticle coming
- MOSFET Small-Signal Model: gm, gdsArticle coming
- MOSFET Structure: Gate, Source, Drain, BodyArticle coming
- Mismatch and Pelgrom Law for AnalogArticle coming
- Mobility Degradation and Strain EngineeringArticle coming
- Monte Carlo Simulation for Yield PredictionArticle coming
- NMOS/PMOS I-V: Triode, Saturation, CutoffArticle coming
- Negative Bias Temperature Instability (NBTI)Article coming
- Noise Margin NMH and NML CalculationArticle coming
- Parasitic Capacitances: Cgg, Cgd, Cgs, CdbArticle coming
- Polysilicon Gate Depletion EffectArticle coming
- Process Corners: TT, FF, SS, SF, FSArticle coming
- Quantum Dot Effects at Sub-3nm NodesArticle coming
- Quantum Mechanical Tunneling in Thin OxidesArticle coming
- Short-Channel Effects: DIBL, Velocity SaturationRead
- Strain Engineering: Biaxial, Uniaxial StressArticle coming
- Sub-Threshold Slope and Leakage CurrentArticle coming
- TCAD Simulation: Sentaurus / Atlas BasicsArticle coming
- Threshold Voltage (VT) and Body EffectArticle coming
- Transconductance gm Bias DependencyArticle coming
- Transmission Gate and Pass Transistor LogicArticle coming
- Well Proximity Effect and Dopant SpreadingArticle coming
Junior Engineer· 0 of 40
- AI-Assisted RTL Generation (Synopsys DSO.ai)Article coming
- AMBA CHI Protocol OverviewArticle coming
- APB and AHB Lite Protocol RTLArticle coming
- AXI4-Lite Protocol RTL ImplementationArticle coming
- AXI4-Stream for Data Path RTLArticle coming
- Arbiter: Round-Robin, Priority, WeightedArticle coming
- Assertion-Based Verification (SVA)Article coming
- Behavioral, Structural, Dataflow ModelingArticle coming
- Blocking vs. Non-Blocking AssignmentsArticle coming
- Branch Predictor and Cache RTL BasicsArticle coming
- Bus Matrix and Crossbar Switch RTLArticle coming
- Clock Domain Crossing Synchronizer DesignArticle coming
- Clock and Reset Strategy in RTLArticle coming
- Combinational Logic in RTL: Priority EncodingArticle coming
- Constrained Random Stimulus GenerationArticle coming
- FIFO Design: Synchronous and AsynchronousArticle coming
- FSM Coding: One-Hot, Gray, BinaryArticle coming
- Functional Coverage and Code CoverageArticle coming
- Hardware Emulation Platforms OverviewArticle coming
- High-Level Synthesis (HLS): Vivado HLSArticle coming
- IP Reuse and Hardening StrategyArticle coming
- Interface and Clocking Block in SVArticle coming
- Mealy vs. Moore State MachineArticle coming
- Open-Source EDA: OpenLane, Sky130 FlowArticle coming
- Parameterized Modules and GenerateArticle coming
- Pipeline Hazard: RAW, WAW, WAR HandlingArticle coming
- Power Management Unit (PMU) RTL DesignArticle coming
- RTL Coding Style: Sync Reset, Clk EnableArticle coming
- RTL Linting Rules and SpyGlass CheckArticle coming
- RTL Power Estimation (Early Stage)Article coming
- RTL Simulation with VCS / ModelSimArticle coming
- Sequential Logic: DFF and Latch DifferencesArticle coming
- Simulation Waveform Analysis and DebugArticle coming
- SoC Top-Level Integration and HierarchyArticle coming
- Synthesis Directives: Preserve, KeepArticle coming
- Testbench Writing: Stimulus, Monitor, CheckerArticle coming
- UVM Architecture: Agent, Sequencer, Driver, MonitorArticle coming
- UVM Register Model (RAL) DesignArticle coming
- VHDL Entity-Architecture-PackageArticle coming
- Verilog: Module, Port, Wire, Reg, AlwaysArticle coming
Middle Engineer· 1 of 80
- ADC: Flash, SAR, Pipeline, Sigma-DeltaArticle coming
- AOCV and POCV for Advanced NodesArticle coming
- Analog Fault Modeling and Test CoverageArticle coming
- Analog Layout: Guard Ring, ShieldingArticle coming
- Analog-Digital Interface Level ShifterArticle coming
- Bandgap Voltage Reference (BGR) DesignArticle coming
- Boolean Optimization: Map, Flatten, CompileArticle coming
- CMOS Comparator: Dynamic, Latch-BasedArticle coming
- Calibration Circuit: Offset, Gain, NonlinearityArticle coming
- Cell Delay Interpolation in LibertyArticle coming
- Charge Pump for Non-Volatile MemoryArticle coming
- Clock Domain Crossing (CDC) Formal CheckArticle coming
- Clock Gating ICG Cell IntegrationArticle coming
- Clock Skew and Useful Skew OptimizationArticle coming
- Common-Centroid and Interdigitated LayoutArticle coming
- Current Mirror: Simple, Cascode, WilsonArticle coming
- DAC: R-2R, Current Steering, Binary WeightedArticle coming
- Datapath Optimization: Adder/Multiplier InferenceArticle coming
- Differential Pair and Tail Current SourceArticle coming
- ECO (Engineering Change Order) ClosureArticle coming
- Folded-Cascode Op-Amp ArchitectureArticle coming
- Formal Equivalence Checking (LEC, Formality)Article coming
- GDS-II Netlist Preparation and FreezeArticle coming
- Glitch Power Reduction via Logic RestructureArticle coming
- Hierarchical STA FlowArticle coming
- High-Fanout Net Buffer Tree SynthesisArticle coming
- Hold Fixing: Buffer Insertion, Delay CellArticle coming
- Hold Slack Distribution AnalysisArticle coming
- IBIS Model for I/O Cell CharacterizationArticle coming
- IEEE 1149.4 Mixed-Signal Boundary ScanArticle coming
- Integer-N and Fractional-N PLL SynthesisArticle coming
- LDO Regulator IC DesignArticle coming
- LTPL / RTPL Path Delay AnalysisArticle coming
- Latch-Based Design Synthesis ChallengesArticle coming
- Liberty (.lib) Characterization File FormatArticle coming
- Logic Synthesis Flow: Design Compiler / GenusArticle coming
- Low-Noise Amplifier (LNA) for RF-CMOSArticle coming
- Mismatch-Induced Offset and CompensationArticle coming
- Mixed-Signal Simulation: AMS, VAMSArticle coming
- Mixer Design: Gilbert Cell, Passive RingArticle coming
- Monte Carlo and Corner Sim for YieldArticle coming
- Multi-Corner Multi-Mode (MCMM) AnalysisArticle coming
- Multi-Voltage Synthesis with UPF Level ShifterArticle coming
- Noise Figure for Cascaded StagesArticle coming
- OTA (Operational Transconductance Amplifier)Article coming
- On-Chip Variation (OCV): Derate FactorsArticle coming
- PLL: VCO, Charge Pump, Loop FilterArticle coming
- PSRR and CMRR of Op-AmpArticle coming
- Parasitic Extraction: StarRC and QuantusArticle coming
- Path Grouping and Exception HandlingArticle coming
- Post-Layout Simulation with PEXArticle coming
- Power Gating Cell Insertion in SynthesisArticle coming
- Power-Aware STA (PrimeTime PX, Voltus)Article coming
- Regulated Cascode and Gain BoostArticle coming
- Retiming for Pipeline ThroughputArticle coming
- SAR ADC Capacitor DAC DesignArticle coming
- SDC: create_clock, set_input_delayArticle coming
- SDC: set_false_path, set_multicycle_pathArticle coming
- STA with Signal Integrity (Crosstalk)Article coming
- Sample-and-Hold Circuit DesignArticle coming
- Scan-Based DFT in Synthesis FlowArticle coming
- SerDes TX/RX Architecture and EqualizationArticle coming
- Setup Fixing: Resizing and RestructuringArticle coming
- Setup Time, Hold Time, Slack CalculationArticle coming
- Sigma-Delta Modulator: NTF and STFArticle coming
- Standard Cell Drive Strength SelectionArticle coming
- Standard Cell Library: Std, IO, MacroArticle coming
- Static Timing Analysis with PrimeTimeArticle coming
- Switched-Capacitor Circuit DesignArticle coming
- Synthesis QoR Metrics: Area, Power, TimingArticle coming
- Temperature Compensation: CTAT and PTATRead
- Temperature Sensor and Voltage Monitor ICArticle coming
- Thermal and Flicker Noise AnalysisArticle coming
- Timing Debug with Timing ReportsArticle coming
- Timing Margin Sign-off CriteriaArticle coming
- Timing Paths and Critical Path AnalysisArticle coming
- Trimming and Calibration in ProductionArticle coming
- Two-Stage Op-Amp with Miller CompensationArticle coming
- VCO Design: Ring, LC, RelaxationArticle coming
- Wideband Baseband Amplifier DesignArticle coming
Senior Engineer· 0 of 40
- AI-Driven Placement and Routing (ML-EDA)Article coming
- Advanced PDK and DRC Deck ManagementArticle coming
- Antenna Rule Checking and Diode InsertionArticle coming
- Bondpad and IO Ring IntegrationArticle coming
- CTS Skew Balancing and OptimizationArticle coming
- Chip Finishing: GDS-II Merge and TapeoutArticle coming
- Chip-Level Assembly FlowArticle coming
- Clock Mesh vs. Balanced H-Tree Trade-offArticle coming
- Clock Tree Synthesis (CTS): H-Tree, MeshArticle coming
- DFM (Design for Manufacturability) RulesArticle coming
- DRC (Design Rule Check) Categories and FixingArticle coming
- DTCO (Design-Technology Co-Optimization)Article coming
- Detailed Routing: Track Assignment, Via OptArticle coming
- ESD Power Clamp PlacementArticle coming
- Electromigration Sign-off: Current DensityArticle coming
- Extraction Accuracy: Calibrated DecksArticle coming
- Filler Cell and Decap InsertionArticle coming
- Floorplanning: Die Area, Aspect Ratio, UtilizationArticle coming
- Full-Chip ESD VerificationArticle coming
- Global Routing: FLUTE, Maze RoutingArticle coming
- Hierarchical Design: Partition, InterfaceArticle coming
- IR Drop Analysis: Static and DynamicArticle coming
- LVS (Layout vs. Schematic) VerificationArticle coming
- Level Shifter Placement and Power GatingArticle coming
- Macro Placement: Timing-Driven, Congestion-AwareArticle coming
- Metal Fill and CMP Density RequirementsArticle coming
- Multi-Patterning: SADP, LELE, Self-AlignedArticle coming
- Multi-Voltage Design Floor PlanArticle coming
- On-Chip Decoupling Capacitor StrategyArticle coming
- Package-Aware Floor PlanningArticle coming
- Physical Hierarchy and Block-Level SignoffArticle coming
- Power Domain Definition (UPF): Power StatesArticle coming
- Power Planning: Rings, Straps, IR DropArticle coming
- Routing in Advanced Nodes: ColoringArticle coming
- Seal Ring and Guard Ring IntegrationArticle coming
- Signal Integrity: Crosstalk in RoutingArticle coming
- Standard Cell Placement: LegalizationArticle coming
- Timing Closure in PnR: Congestion AvoidanceArticle coming
- Track-Based Routing for Advanced NodesArticle coming
- Via Pillars and Via OptimizationArticle coming
Staff Engineer· 0 of 40
- AI-Assisted Coverage ClosureArticle coming
- AMS Simulation Sign-offArticle coming
- ATPG Flow and Fault Coverage TargetArticle coming
- Antenna Effect VerificationArticle coming
- At-Speed Test: IDDQ, Transition FaultArticle coming
- Automotive-Grade Qualification (AEC-Q100)Article coming
- Boundary Scan JTAG IEEE 1149.1Article coming
- Constrained Random Regression SimulationArticle coming
- ERC for Full Chip VerificationArticle coming
- Electromigration and TDDB Silicon DataArticle coming
- Fault Models: Stuck-At, Transition, Path-DelayArticle coming
- Fault Simulation (TetraMAX, Mentor FaultSim)Article coming
- Formal CDC Verification (Jasper CDC App)Article coming
- Formal Equivalence (Conformal LEC)Article coming
- Formal Property Checking (JasperGold)Article coming
- Functional Coverage: Covergroup, CoverpointArticle coming
- Functional Safety Verification (Formal+Sim)Article coming
- ISO 26262 ASIL-B/C/D for ICsArticle coming
- Logic BIST (LBIST) ArchitectureArticle coming
- Memory BIST (MBIST) Controller DesignArticle coming
- Multi-Die Chiplet Test Strategy (IEEE P1838)Article coming
- Post-Silicon Validation and Bring-Up PlanArticle coming
- Power Intent Verification (UPF LP Sign-off)Article coming
- Quality and Outgoing Quality Level (OQL)Article coming
- Quantum Chip Characterization MethodsArticle coming
- Reliability Stress Tests: HTOL, HASTArticle coming
- STA Sign-off Correlation Between ToolsArticle coming
- Safety Island and Lockstep Core ArchitectureArticle coming
- Scan Chain Insertion and DFT CompilerArticle coming
- Scan Compression (XTOL)Article coming
- Silicon Correlation and Yield EnhancementArticle coming
- Silicon Debug: Logic Analyzer, JTAG, ScanArticle coming
- Silicon Lifecycle Management (SLM)Article coming
- Structural Test for 3D-IC TSVArticle coming
- Test Coverage Dashboard and Escape RateArticle coming
- Test Data Volume Compression (EDT)Article coming
- UVM Methodology: Agent, Scoreboard, CoverageArticle coming
- UVM Register Model (RAL) VerificationArticle coming
- Yield Enhancement Tapeout StrategyArticle coming
- iJTAG IEEE 1687 Embedded InstrumentsArticle coming
Distinguished Engineer· 0 of 40
- 2.5D Integration: Interposer, CoWoS, EMIBArticle coming
- 3D NAND Flash Architecture OverviewArticle coming
- 3D-IC: Hybrid Bonding, W2W, D2W BondingArticle coming
- 7nm / 5nm / 3nm Process Node OverviewArticle coming
- AI Accelerator ASIC Architecture (TPU, Groq)Article coming
- AI-Driven Physical Design (ML for PD)Article coming
- Analog Design at 3nm: ChallengesArticle coming
- Backside Power Delivery Network (BSPDN)Article coming
- Beyond-CMOS: RRAM, PCM, SpintronicsArticle coming
- CFET (Complementary FET) Vertical StackingArticle coming
- Carbon Nanotube FET (CNFET) TechnologyArticle coming
- Chiplet Architecture and UCIe StandardArticle coming
- Cryogenic CMOS for Quantum ComputingArticle coming
- DTCO Roadmap: 2nm and BeyondArticle coming
- Disaggregated SoC Architecture StrategyArticle coming
- EUV High-NA 0.55 NA Impact on DesignArticle coming
- EUV Lithography: Source, Optics, ResistArticle coming
- Embedded MRAM (eMRAM) at Advanced NodesArticle coming
- Fan-Out WLP (FOWLP) and InFO PackagingArticle coming
- FinFET vs. GAAFET Nanosheet PhysicsArticle coming
- Gate-All-Around (GAA) ManufacturingArticle coming
- HBM 2E/3/3E Integration on 2.5DArticle coming
- In-Memory Computing ArchitectureArticle coming
- Monolithic 3D Integration (Sequential)Article coming
- Multi-Patterning Complexity at Sub-7nmArticle coming
- Neuromorphic Chip Architecture (Loihi 2)Article coming
- Open Standards: JEDEC HBM, MIPI, PCIe 6.0Article coming
- Open-Source EDA: OpenROAD, OpenLaneArticle coming
- Optical Transceiver on CMOSArticle coming
- Photonic Integrated Circuit (PIC) Co-DesignArticle coming
- Post-Quantum Crypto Hardware AcceleratorArticle coming
- Quantum Dot Technology ApplicationsArticle coming
- RISC-V Vector Extension for AIArticle coming
- SRAM Stability at Advanced Nodes (6T, 8T)Article coming
- Silicon Photonics Waveguide and ModulatorArticle coming
- Sub-1nm Device Research (IMEC, TSMC)Article coming
- Superconducting Qubits and CMOS ControlArticle coming
- Sustainable Chip Design EfficiencyArticle coming
- Technology Roadmap Strategy PlanningArticle coming
- eFuse and OTP Non-Volatile MemoryArticle coming
