VLSI & Chip Design
CMOS device physics, RTL/HDL design, logic synthesis, STA, analog IC, physical design (PnR), DFT, and advanced nodes.
280 topics · 0 with articles
Intern Engineer· 40
- Band-to-Band Tunneling in Ultra-Thin Devices
- Body Bias (FBB, RBB) for Power-Performance
- CMOS Dynamic Power: Switching, Short-Circuit
- CMOS Inverter: Static Transfer Characteristic
- CMOS NAND / NOR Gate Sizing
- CMOS Static Power: Subthreshold, Gate, GIDL
- Channel Length Modulation Lambda
- Contact and Via Resistance Modeling
- Device Characterization: Id-Vgs, Id-Vds Curves
- Dopant Profiling: SIMS Measurement
- ESD Structures: Diode, GGNMOS, SCR
- Electromigration: Blacks Equation
- FinFET Device Physics vs. Planar MOSFET
- Gate Oxide Reliability: TDDB and SILC
- Gate-All-Around (GAA) Nanosheet Physics
- High-k / Metal Gate Stack (HKMG)
- Hot Carrier Injection (HCI) Mechanism
- Interconnect RC Delay: Elmore Model
- Latch-Up Mechanism and Guard Ring Design
- MOSFET Small-Signal Model: gm, gds
- MOSFET Structure: Gate, Source, Drain, Body
- Mismatch and Pelgrom Law for Analog
- Mobility Degradation and Strain Engineering
- Monte Carlo Simulation for Yield Prediction
- NMOS/PMOS I-V: Triode, Saturation, Cutoff
- Negative Bias Temperature Instability (NBTI)
- Noise Margin NMH and NML Calculation
- Parasitic Capacitances: Cgg, Cgd, Cgs, Cdb
- Polysilicon Gate Depletion Effect
- Process Corners: TT, FF, SS, SF, FS
- Quantum Dot Effects at Sub-3nm Nodes
- Quantum Mechanical Tunneling in Thin Oxides
- Short-Channel Effects: DIBL, Velocity Saturation
- Strain Engineering: Biaxial, Uniaxial Stress
- Sub-Threshold Slope and Leakage Current
- TCAD Simulation: Sentaurus / Atlas Basics
- Threshold Voltage (VT) and Body Effect
- Transconductance gm Bias Dependency
- Transmission Gate and Pass Transistor Logic
- Well Proximity Effect and Dopant Spreading
Junior Engineer· 40
- AI-Assisted RTL Generation (Synopsys DSO.ai)
- AMBA CHI Protocol Overview
- APB and AHB Lite Protocol RTL
- AXI4-Lite Protocol RTL Implementation
- AXI4-Stream for Data Path RTL
- Arbiter: Round-Robin, Priority, Weighted
- Assertion-Based Verification (SVA)
- Behavioral, Structural, Dataflow Modeling
- Blocking vs. Non-Blocking Assignments
- Branch Predictor and Cache RTL Basics
- Bus Matrix and Crossbar Switch RTL
- Clock Domain Crossing Synchronizer Design
- Clock and Reset Strategy in RTL
- Combinational Logic in RTL: Priority Encoding
- Constrained Random Stimulus Generation
- FIFO Design: Synchronous and Asynchronous
- FSM Coding: One-Hot, Gray, Binary
- Functional Coverage and Code Coverage
- Hardware Emulation Platforms Overview
- High-Level Synthesis (HLS): Vivado HLS
- IP Reuse and Hardening Strategy
- Interface and Clocking Block in SV
- Mealy vs. Moore State Machine
- Open-Source EDA: OpenLane, Sky130 Flow
- Parameterized Modules and Generate
- Pipeline Hazard: RAW, WAW, WAR Handling
- Power Management Unit (PMU) RTL Design
- RTL Coding Style: Sync Reset, Clk Enable
- RTL Linting Rules and SpyGlass Check
- RTL Power Estimation (Early Stage)
- RTL Simulation with VCS / ModelSim
- Sequential Logic: DFF and Latch Differences
- Simulation Waveform Analysis and Debug
- SoC Top-Level Integration and Hierarchy
- Synthesis Directives: Preserve, Keep
- Testbench Writing: Stimulus, Monitor, Checker
- UVM Architecture: Agent, Sequencer, Driver, Monitor
- UVM Register Model (RAL) Design
- VHDL Entity-Architecture-Package
- Verilog: Module, Port, Wire, Reg, Always
Middle Engineer· 80
- ADC: Flash, SAR, Pipeline, Sigma-Delta
- AOCV and POCV for Advanced Nodes
- Analog Fault Modeling and Test Coverage
- Analog Layout: Guard Ring, Shielding
- Analog-Digital Interface Level Shifter
- Bandgap Voltage Reference (BGR) Design
- Boolean Optimization: Map, Flatten, Compile
- CMOS Comparator: Dynamic, Latch-Based
- Calibration Circuit: Offset, Gain, Nonlinearity
- Cell Delay Interpolation in Liberty
- Charge Pump for Non-Volatile Memory
- Clock Domain Crossing (CDC) Formal Check
- Clock Gating ICG Cell Integration
- Clock Skew and Useful Skew Optimization
- Common-Centroid and Interdigitated Layout
- Current Mirror: Simple, Cascode, Wilson
- DAC: R-2R, Current Steering, Binary Weighted
- Datapath Optimization: Adder/Multiplier Inference
- Differential Pair and Tail Current Source
- ECO (Engineering Change Order) Closure
- Folded-Cascode Op-Amp Architecture
- Formal Equivalence Checking (LEC, Formality)
- GDS-II Netlist Preparation and Freeze
- Glitch Power Reduction via Logic Restructure
- Hierarchical STA Flow
- High-Fanout Net Buffer Tree Synthesis
- Hold Fixing: Buffer Insertion, Delay Cell
- Hold Slack Distribution Analysis
- IBIS Model for I/O Cell Characterization
- IEEE 1149.4 Mixed-Signal Boundary Scan
- Integer-N and Fractional-N PLL Synthesis
- LDO Regulator IC Design
- LTPL / RTPL Path Delay Analysis
- Latch-Based Design Synthesis Challenges
- Liberty (.lib) Characterization File Format
- Logic Synthesis Flow: Design Compiler / Genus
- Low-Noise Amplifier (LNA) for RF-CMOS
- Mismatch-Induced Offset and Compensation
- Mixed-Signal Simulation: AMS, VAMS
- Mixer Design: Gilbert Cell, Passive Ring
- Monte Carlo and Corner Sim for Yield
- Multi-Corner Multi-Mode (MCMM) Analysis
- Multi-Voltage Synthesis with UPF Level Shifter
- Noise Figure for Cascaded Stages
- OTA (Operational Transconductance Amplifier)
- On-Chip Variation (OCV): Derate Factors
- PLL: VCO, Charge Pump, Loop Filter
- PSRR and CMRR of Op-Amp
- Parasitic Extraction: StarRC and Quantus
- Path Grouping and Exception Handling
- Post-Layout Simulation with PEX
- Power Gating Cell Insertion in Synthesis
- Power-Aware STA (PrimeTime PX, Voltus)
- Regulated Cascode and Gain Boost
- Retiming for Pipeline Throughput
- SAR ADC Capacitor DAC Design
- SDC: create_clock, set_input_delay
- SDC: set_false_path, set_multicycle_path
- STA with Signal Integrity (Crosstalk)
- Sample-and-Hold Circuit Design
- Scan-Based DFT in Synthesis Flow
- SerDes TX/RX Architecture and Equalization
- Setup Fixing: Resizing and Restructuring
- Setup Time, Hold Time, Slack Calculation
- Sigma-Delta Modulator: NTF and STF
- Standard Cell Drive Strength Selection
- Standard Cell Library: Std, IO, Macro
- Static Timing Analysis with PrimeTime
- Switched-Capacitor Circuit Design
- Synthesis QoR Metrics: Area, Power, Timing
- Temperature Compensation: CTAT and PTAT
- Temperature Sensor and Voltage Monitor IC
- Thermal and Flicker Noise Analysis
- Timing Debug with Timing Reports
- Timing Margin Sign-off Criteria
- Timing Paths and Critical Path Analysis
- Trimming and Calibration in Production
- Two-Stage Op-Amp with Miller Compensation
- VCO Design: Ring, LC, Relaxation
- Wideband Baseband Amplifier Design
Senior Engineer· 40
- AI-Driven Placement and Routing (ML-EDA)
- Advanced PDK and DRC Deck Management
- Antenna Rule Checking and Diode Insertion
- Bondpad and IO Ring Integration
- CTS Skew Balancing and Optimization
- Chip Finishing: GDS-II Merge and Tapeout
- Chip-Level Assembly Flow
- Clock Mesh vs. Balanced H-Tree Trade-off
- Clock Tree Synthesis (CTS): H-Tree, Mesh
- DFM (Design for Manufacturability) Rules
- DRC (Design Rule Check) Categories and Fixing
- DTCO (Design-Technology Co-Optimization)
- Detailed Routing: Track Assignment, Via Opt
- ESD Power Clamp Placement
- Electromigration Sign-off: Current Density
- Extraction Accuracy: Calibrated Decks
- Filler Cell and Decap Insertion
- Floorplanning: Die Area, Aspect Ratio, Utilization
- Full-Chip ESD Verification
- Global Routing: FLUTE, Maze Routing
- Hierarchical Design: Partition, Interface
- IR Drop Analysis: Static and Dynamic
- LVS (Layout vs. Schematic) Verification
- Level Shifter Placement and Power Gating
- Macro Placement: Timing-Driven, Congestion-Aware
- Metal Fill and CMP Density Requirements
- Multi-Patterning: SADP, LELE, Self-Aligned
- Multi-Voltage Design Floor Plan
- On-Chip Decoupling Capacitor Strategy
- Package-Aware Floor Planning
- Physical Hierarchy and Block-Level Signoff
- Power Domain Definition (UPF): Power States
- Power Planning: Rings, Straps, IR Drop
- Routing in Advanced Nodes: Coloring
- Seal Ring and Guard Ring Integration
- Signal Integrity: Crosstalk in Routing
- Standard Cell Placement: Legalization
- Timing Closure in PnR: Congestion Avoidance
- Track-Based Routing for Advanced Nodes
- Via Pillars and Via Optimization
Staff Engineer· 40
- AI-Assisted Coverage Closure
- AMS Simulation Sign-off
- ATPG Flow and Fault Coverage Target
- Antenna Effect Verification
- At-Speed Test: IDDQ, Transition Fault
- Automotive-Grade Qualification (AEC-Q100)
- Boundary Scan JTAG IEEE 1149.1
- Constrained Random Regression Simulation
- ERC for Full Chip Verification
- Electromigration and TDDB Silicon Data
- Fault Models: Stuck-At, Transition, Path-Delay
- Fault Simulation (TetraMAX, Mentor FaultSim)
- Formal CDC Verification (Jasper CDC App)
- Formal Equivalence (Conformal LEC)
- Formal Property Checking (JasperGold)
- Functional Coverage: Covergroup, Coverpoint
- Functional Safety Verification (Formal+Sim)
- ISO 26262 ASIL-B/C/D for ICs
- Logic BIST (LBIST) Architecture
- Memory BIST (MBIST) Controller Design
- Multi-Die Chiplet Test Strategy (IEEE P1838)
- Post-Silicon Validation and Bring-Up Plan
- Power Intent Verification (UPF LP Sign-off)
- Quality and Outgoing Quality Level (OQL)
- Quantum Chip Characterization Methods
- Reliability Stress Tests: HTOL, HAST
- STA Sign-off Correlation Between Tools
- Safety Island and Lockstep Core Architecture
- Scan Chain Insertion and DFT Compiler
- Scan Compression (XTOL)
- Silicon Correlation and Yield Enhancement
- Silicon Debug: Logic Analyzer, JTAG, Scan
- Silicon Lifecycle Management (SLM)
- Structural Test for 3D-IC TSV
- Test Coverage Dashboard and Escape Rate
- Test Data Volume Compression (EDT)
- UVM Methodology: Agent, Scoreboard, Coverage
- UVM Register Model (RAL) Verification
- Yield Enhancement Tapeout Strategy
- iJTAG IEEE 1687 Embedded Instruments
Distinguished Engineer· 40
- 2.5D Integration: Interposer, CoWoS, EMIB
- 3D NAND Flash Architecture Overview
- 3D-IC: Hybrid Bonding, W2W, D2W Bonding
- 7nm / 5nm / 3nm Process Node Overview
- AI Accelerator ASIC Architecture (TPU, Groq)
- AI-Driven Physical Design (ML for PD)
- Analog Design at 3nm: Challenges
- Backside Power Delivery Network (BSPDN)
- Beyond-CMOS: RRAM, PCM, Spintronics
- CFET (Complementary FET) Vertical Stacking
- Carbon Nanotube FET (CNFET) Technology
- Chiplet Architecture and UCIe Standard
- Cryogenic CMOS for Quantum Computing
- DTCO Roadmap: 2nm and Beyond
- Disaggregated SoC Architecture Strategy
- EUV High-NA 0.55 NA Impact on Design
- EUV Lithography: Source, Optics, Resist
- Embedded MRAM (eMRAM) at Advanced Nodes
- Fan-Out WLP (FOWLP) and InFO Packaging
- FinFET vs. GAAFET Nanosheet Physics
- Gate-All-Around (GAA) Manufacturing
- HBM 2E/3/3E Integration on 2.5D
- In-Memory Computing Architecture
- Monolithic 3D Integration (Sequential)
- Multi-Patterning Complexity at Sub-7nm
- Neuromorphic Chip Architecture (Loihi 2)
- Open Standards: JEDEC HBM, MIPI, PCIe 6.0
- Open-Source EDA: OpenROAD, OpenLane
- Optical Transceiver on CMOS
- Photonic Integrated Circuit (PIC) Co-Design
- Post-Quantum Crypto Hardware Accelerator
- Quantum Dot Technology Applications
- RISC-V Vector Extension for AI
- SRAM Stability at Advanced Nodes (6T, 8T)
- Silicon Photonics Waveguide and Modulator
- Sub-1nm Device Research (IMEC, TSMC)
- Superconducting Qubits and CMOS Control
- Sustainable Chip Design Efficiency
- Technology Roadmap Strategy Planning
- eFuse and OTP Non-Volatile Memory