Digital Electronics
Logic design, combinational/sequential circuits, digital arithmetic, HDL design, and digital system architecture.
400 topics · 0 with articles
Intern Engineer· 80
- ASCII, Unicode, and Character Encoding Standards
- Arithmetic Shifts vs. Logical Shifts
- BCD (Binary-Coded Decimal): Packed and Unpacked
- BCD Adder: Sum Correction for BCD Output
- Barrel Shifter Operation and Applications
- Barrel Shifter: Combinational Shift by N Bits
- Binary Division: Restoring and Non-Restoring Methods
- Binary Multiplication: Partial Products Method
- Binary Number System: Bit, Byte, Word, MSB, LSB
- Binary-to-Hex and Hex-to-Binary Shortcuts
- Bitwise Operations: Masking, Setting, Clearing, Toggling
- Boolean Algebra: AND, OR, NOT, NAND, NOR, XOR, XNOR
- Boolean Identities and Theorems (De Morgan's Laws)
- Booth's Algorithm for Signed Multiplication
- CMOS Logic: Fan-Out, Noise Margin, Power Dissipation
- CMOS Transmission Gate: Pass Transistor Logic
- Canonical POS (Product of Sums) Form
- Canonical SOP (Sum of Products) Form
- Carry Look-Ahead Adder (CLA): Group Propagate and Generate
- Carry-Ripple vs. Carry-Look-Ahead Trade-off
- Carry-Save Adder (CSA) for Multiplier Trees
- Combinational Logic Power: Cv²f and Short-Circuit Power
- Comparator: 1-bit, 4-bit Magnitude Comparison
- Critical Path Analysis in Combinational Circuits
- Crossbar Switch (Permutation Network) Architecture
- Cyclic Redundancy Check (CRC) Polynomial Division
- Decimal to Binary Conversion and Vice Versa
- Decoder: 2-to-4, 3-to-8 Active-High and Active-Low
- Demultiplexer (DEMUX): 1:2, 1:4, 1:8 Decoder Function
- Duality Principle in Boolean Algebra
- Encoder: Priority Encoder (4-to-2, 8-to-3)
- Error-Correcting Codes (ECC): Hamming Distance Concept
- Excess-3 (XS-3) Code for BCD Arithmetic
- Fixed-Point Number Representation: Q-Format (Qm.n)
- Floating-Point Rounding Modes (Round-to-Nearest, Truncate)
- Full Adder: Sum, Carry-In, and Carry-Out
- Gate-Level Schematic: Symbols and Truth Tables
- Glitch Power in Combinational Logic and Mitigation
- Gray Code: Definition, Encoding, and Applications
- Half Adder: Sum and Carry Logic
- Hamming Code: Error Detection and Correction Basics
- Hazard Elimination: Redundant Gate Technique
- Hazards in Combinational Logic: Static-0, Static-1, Dynamic
- IEEE 754 Floating-Point: Single and Double Precision
- IEEE 754 Special Values: NaN, Infinity, Denormals
- Integer Division: Array Divider and SRT Algorithm
- K-Map: Grouping Rules, Don't-Care Conditions
- Karnaugh Map (K-Map): 2, 3, 4, 5-Variable Simplification
- Logic Families: CMOS, TTL, ECL, and Key Parameters
- Logic Function Minimization for Cost and Speed
- Logic Gates: AND, OR, NOT, NAND, NOR, XOR, XNOR
- Logic Levels: VIL, VIH, VOL, VOH and Noise Margins
- MUX-Based Function Generator: Any Boolean Function
- Minterm and Maxterm Notation
- Multiplexer (MUX): 2:1, 4:1, 8:1 and Enable Control
- Number System Conversion Table Quick Reference
- Octal and Hexadecimal Number Systems
- One's Complement: Definition and Subtraction
- Ones-Count / Population Count (Popcount) Operation
- Overflow and Underflow in Fixed-Width Arithmetic
- Parallel Prefix Adder: Kogge-Stone, Brent-Kung, Han-Carlson
- Parity Bit: Even and Odd Parity Generation
- Positive vs. Negative Logic Convention
- Priority Encoder Application: Interrupt Controller
- Programmable Logic Array (PLA) and PAL
- Propagation Delay (tpd), Contamination Delay (tcd)
- Quine-McCluskey (Tabular) Minimization Method
- ROM as Combinational Logic LUT Implementation
- Ripple Carry Adder (RCA): Propagation Delay Analysis
- Shannon's Expansion Theorem
- Signed Integer Representation: Sign-Magnitude
- Standard Cell Library: Drive Strength and Delay Modeling
- Subtractor: Half and Full Subtractor Using Complement
- Technology Mapping: NAND2/INV Gate Implementation
- Tri-State (Three-State) Buffer and Bus Architecture
- Two's Complement: Representation and Arithmetic
- Universal Gates: NAND-Only and NOR-Only Implementations
- Wallace Tree Multiplier Architecture
- Wired Logic and Open-Drain / Open-Collector Gates
- Wired-AND and Wired-OR (Open-Collector) Logic
Junior Engineer· 40
- Asynchronous FIFO: Write Pointer, Read Pointer, Empty/Full
- BCD Counter (Decade Counter): 0–9 Sequence
- Clock Domain Crossing (CDC): FIFO, Handshake, Bus Encoding
- Clock Gating for Sequential Power Reduction
- Clock Jitter: Cycle-to-Cycle and Long-Term Accumulated
- Clock Skew and Its Effect on Setup and Hold Margins
- Counter Design: Ripple (Asynchronous) Counter
- D Flip-Flop: Rising-Edge Triggered, Timing Parameters
- D Latch: Transparent and Opaque Operation
- FSM Design: State Diagram, State Table, Next-State Logic
- FSM Optimization: State Minimization (Implication Table)
- FSM State Encoding: Binary, One-Hot, Gray Code
- Finite State Machine (FSM): Mealy vs. Moore Architecture
- Gray-Code Encoded FIFO for CDC
- Hold Time Constraint: tckq + tcd ≥ th
- JK Flip-Flop: Truth Table and Toggle Mode
- LFSR Maximal-Length Sequence (m-Sequence) Properties
- Latches vs. Flip-Flops: Level-Sensitive vs. Edge-Triggered
- Linear Feedback Shift Register (LFSR): Polynomial Taps
- Low-Power State Retention Flip-Flop with Balloon Latch
- Memory Element Comparison: SRAM Cell vs. DRAM Cell
- Metastability: MTBF Calculation and Synchronizer Design
- Modulo-N Counter: Synchronous and Asynchronous Reset
- Pipeline Register Insertion for Retiming
- Power in Sequential Logic: Clock Tree, Flip-Flop Switching
- Register File: Read and Write Port Architecture
- Retiming: Moving Registers Across Combinational Logic
- Ring Counter and Johnson (Twisted-Ring) Counter
- SR Latch: NAND and NOR Implementations, Forbidden State
- Setup Time (tsu), Hold Time (th), Clock-to-Q Delay (tckq)
- Shift Register Applications: Serial-to-Parallel Conversion
- Shift Register: Serial-In Serial-Out (SISO), SIPO, PISO, PIPO
- Synchronizer Design: Double-Register (2-FF) Synchronizer
- Synchronous Down-Counter and Up-Down Counter
- Synchronous FIFO: Depth Calculation, Status Flags
- Synchronous Reset vs. Asynchronous Reset Flip-Flop
- Synchronous Up-Counter: D-FF and Combinational Logic
- T Flip-Flop: Toggle Operation and Counter Application
- Timing Analysis: False Paths and Multicycle Paths
- Timing Constraints: Setup Slack = Tclock - tckq - tpd - tsu
Middle Engineer· 120
- 3D NAND Flash: Vertical Channel, Layer Count (128+)
- AXI4-Lite Protocol RTL: Ready/Valid Handshake
- AXI4-Stream RTL: TDATA, TVALID, TREADY, TLAST
- Arbiter RTL Design: Round-Robin, Priority
- BRAM Inference vs. Instantiation Trade-offs
- Block RAM (BRAM): True Dual-Port, Simple Dual-Port, SDP
- Blocking (=) vs. Non-Blocking (<=) Assignment Rules
- Cache Coherence Protocols: MESI, MOESI, MESIF
- Cache Memory Architecture: Direct-Mapped, Set-Associative, Fully-Associative
- Cache Replacement Policies: LRU, LFU, FIFO, Random
- Catapult HLS / Vivado HLS Directives and Pragmas
- Chip-Level Power Estimation: XPower, Intel PowerPlay
- ChipScope / Signal Tap / Reveal: In-System Debug
- Clock Gating RTL: ICG Cell and Enable Flop
- Constraint File (SDC): create_clock, set_input_delay
- Constraint-Driven Design: XDC and QSF Constraint Files
- Content-Addressable Memory (CAM): TCAM for Routing Tables
- Continuous Assignment (assign): Combinational Modeling
- DDR4 SDRAM: Differential Clock, Data Strobe (DQS), ODT
- DDR5: Inline ECC, Decision Feedback Equalization (DFE)
- DRAM Addressing: Row Address Strobe (RAS) and CAS
- DRAM Cell: 1T1C Structure, Capacitor Charge Retention
- DRAM Refresh: tREF, tRFC, Distributed vs. Burst Refresh
- DSP Slice Cascading for High-Precision Arithmetic
- DSP48 / DSP Slice: Multiply-Accumulate (MAC) Operation
- Distributed RAM: LUT-Based RAM in Slice
- ECC DRAM: SECDED, Chipkill Correction
- EEPROM: Byte-Erasable, Endurance, Data Retention Specs
- Emerging NVM: MRAM (Magnetoresistive RAM) Properties
- FIFO Generator IP: Common Clock and Independent Clock
- FIFO RTL Design: Pointer Arithmetic, Flags
- FPGA Anti-Tamper and Configuration Security
- FPGA Architecture: LUT, Flip-Flop, BRAM, DSP, IO Blocks
- FPGA Clock Resources: MMCM, PLL, Global/Regional Buffers
- FPGA Configuration: JTAG, SPI Flash, SelectMAP, USB
- FPGA I/O Standards: LVCMOS, LVDS, HSTL, SSTL
- FPGA Machine Learning Inference: Vitis AI, hls4ml
- FPGA Place and Route: Floorplanning, Pipelining for Fmax
- FPGA Power Optimization: Logic, Routing, I/O, Static
- FPGA Prototyping of ASIC / SoC Designs
- FPGA Routing: Switch Matrix, Connection Boxes, Routing Channels
- FPGA Security: Bitstream Encryption and Authentication
- FPGA Soft-Core Processors: MicroBlaze, NIOS II, RISC-V
- FSM Coding in Verilog: One-Hot, Binary, Two-Process Style
- FeRAM (Ferroelectric RAM): Polarization Switching
- Flash Controller: FTL (Flash Translation Layer) Design
- Flash ECC: BCH, LDPC for Error Correction
- Flash Wear Leveling: Static, Dynamic, Global Algorithms
- For-Generate and If-Generate Constructs
- GDDR6: Graphics Memory Bandwidth and PAM4 Signaling
- HBM (High Bandwidth Memory): Silicon Interposer, TSV
- HLS IP Integration in Vivado / Quartus
- Hierarchical Design: Module Instantiation, Port Mapping
- High-Level Design: OpenCL on FPGA (Intel oneAPI, Vitis HLS)
- High-Level Synthesis (HLS): C++ to RTL Flow Overview
- High-Speed Transceiver (GTX, GTP, GTH): SerDes Basics
- Intel Agilex: Heterogeneous Tiles and HBM Integration
- Intel Quartus Prime: Compilation, Timing Analysis
- JTAG AXI Master: On-Chip Debug Without External Probe
- LPDDR5: Low-Power DRAM for Mobile and Wearable
- Lattice Diamond and Radiant Tools Overview
- Look-Up Table (LUT): N-Input Function Implementation
- MRAM STT-MRAM: Write Energy and Read Disturb
- Memory Bandwidth and Latency Trade-offs
- Memory Controller in FPGA: DDR4/LPDDR4 MIG IP
- Memory Hierarchy: L1, L2, L3 Cache and Main Memory
- Multi-FPGA Partitioning and Inter-FPGA Interface
- NAND Flash: Page, Block, Plane Hierarchy and Erase Cycle
- NOR Flash Memory: Random Access, Execute-in-Place (XIP)
- NVMe Protocol over PCIe: Command Queue and Low Latency
- Named vs. Positional Port Connection
- Open-Source FPGA Toolchain: Yosys, nextpnr, OpenFPGA
- PCIe Hard IP Core in FPGA: Endpoint Configuration
- Parameterized Modules and VHDL Generics
- Partial Reconfiguration (PR): Dynamic Region Design
- Phase Change Memory (PCM / 3D XPoint): Set/Reset
- Pipeline RTL Design: Stall, Flush, Hazard Handling
- Procedural Blocks: always @(*) for Combinational Logic
- Processing in Memory (PIM / PNM): Computational Storage
- ROM Types: Mask ROM, OTP PROM, EPROM, EEPROM
- RRAM / Memristor: Resistive Switching Mechanism
- RTL Coding Guidelines: Reset Strategy, Coding Style
- RTL Linting: Common Warnings and Error Classes
- RTL for Memories: Synchronous Read, Write Enable
- SDC: set_false_path, set_multicycle_path, set_max_delay
- SDRAM: Synchronous Operation, Burst Mode, Bank Architecture
- SLC, MLC, TLC, QLC NAND: Bits-per-Cell Trade-offs
- SRAM Cell: 6-Transistor (6T) Structure and Operation
- SRAM Read Operation: Bit-Line Precharge and Sense Amplifier
- SRAM Speed vs. Area Trade-off: Cell Sizing
- SRAM Stability: Static Noise Margin (SNM) Butterfly Curve
- SRAM Write Operation: Write Driver and Word Line
- SRAM vs. DRAM vs. Flash vs. NVM Comparison Matrix
- Scratchpad Memory in Embedded Processors
- Sequential Procedural Block: always @(posedge clk)
- Simulation Delta Cycle and Event-Driven Semantics
- Synthesis-Friendly RTL: Inferred Latches, Unintended Loops
- SystemVerilog Data Types: logic, bit, int, shortreal
- SystemVerilog Interfaces and Modport
- SystemVerilog Packages and Typedef
- Timing Closure: Critical Path, Register Retiming
- VHDL 2008 and SystemVerilog 2012 Key Enhancements
- VHDL Data Types: std_logic, std_logic_vector, unsigned, signed
- VHDL Entity and Architecture: Signal, Variable, Constant
- VHDL Process Statement: Sensitivity List and Wait
- VHDL if-elsif-else and case Statement
- Verilog Data Types: wire, reg, integer, real, time
- Verilog Module Declaration: port, wire, reg, parameter
- Verilog Operators: Arithmetic, Logical, Bitwise, Reduction
- Verilog Packages and VHDL Package / Library Use
- Verilog Testbench Structure: DUT, Clock Gen, Stimulus
- Verilog if-else and case / casex / casez Statements
- Verilog vs. VHDL: Language Philosophy and Key Differences
- Version Control for RTL: Git Workflow and Review
- Xilinx CLB / Altera (Intel) ALM Architecture
- Xilinx Vivado Design Suite: Project and IP Flow
- Xilinx Zynq: PS (ARM) and PL (FPGA) Integration
- Zynq UltraScale+ MPSoC: Quad-Core ARM + FPGA
- eFPGA Embedded in SoC: Fabric Integration Challenges
- eMMC and UFS: Embedded Flash Storage Interfaces
Senior Engineer· 80
- AI Inference Accelerator: MAC Array and Data Flow
- Activity-Driven Power Analysis: Switching Activity Files (SAIF)
- Adaptive Voltage Scaling (AVS): Body Bias and Voltage Tune
- Adiabatic Logic: Energy-Recovering Switching Technique
- Approximate Computing: Bit-Width Truncation, Voltage Scaling
- Array Multiplier: Partial Product Generation and Summation
- Asynchronous (Clockless) Logic: Handshake Protocols
- Binary Addition: Half Adder, Full Adder, Carry Propagation
- Body Biasing: Forward Body Bias (FBB) and RBB for Leakage
- Booth's Algorithm: Radix-2 Signed Multiplication
- CIC (Cascaded Integrator-Comb) Filter Hardware
- CORDIC Algorithm: Rotation Mode for Sin, Cos, Arctan
- CORDIC Vectoring Mode: Magnitude and Phase Computation
- CPF (Common Power Format): Alternative Power Spec
- Carry Look-Ahead Adder (CLA): G and P Terms
- Clock Gating: Integrated Clock Gate (ICG) Cell Usage
- DDS (Direct Digital Synthesis): Spurious Performance
- Data Gating: Suppressing Transitions in Unused Data Paths
- Digital Mixer: I/Q Downconversion and Upconversion
- Dynamic Power: P = α C V² f (Activity, Cap, Voltage, Freq)
- Dynamic Voltage and Frequency Scaling (DVFS)
- Electromigration (EM): Current Density Limits in Metal
- Energy-Quality Scaling in Deep Learning Accelerators
- FFT Hardware Architecture: Radix-2 Butterfly Units
- FIR Filter Direct-Form Hardware Implementation
- FIR Filter Polyphase Decomposition for Downsampling
- FIR Filter Transposed-Form for Reduced Critical Path
- Fixed-Point DSP: Quantization Error and Dynamic Range
- Floating-Point Addition: Alignment, Addition, Normalization
- Floating-Point Division: Newton-Raphson Iteration
- Floating-Point Multiplication: Mantissa Multiply, Exp Add
- Gate Leakage: Quantum Tunneling Through Thin Gate Oxide
- Globally Asynchronous Locally Synchronous (GALS) Design
- Half-Band FIR Filter: Efficient Decimation by 2
- High-Vt Cells for Leakage Reduction in Non-Critical Paths
- IFFT for OFDM Symbol Generation
- IIR Biquad Section (SOS) for Cascade Implementation
- IIR Filter: Direct Form I and II Hardware Realization
- IR Drop Analysis: Static (STA-Based) and Dynamic (Transient)
- Integer Division: Restoring and Non-Restoring Algorithm
- Isolation Cell: Clamping Power Domain Outputs to Logic Level
- Junction Leakage: Reverse-Biased Diode Current
- LDPC Decoder: Check Node and Variable Node Processing
- Level Shifter: Low-to-High and High-to-Low Conversion
- Long-Channel Devices for Ultra-Low Leakage
- Low-Power Memory: SRAM with Dual-Rail, Assist Techniques
- Mobile SoC Power Management: PMIC Collaboration, DVFS Profiles
- Modified Booth Encoding: Radix-4 for Faster Multiply
- Multi-Vt (Threshold Voltage) Cell Library Strategy
- NCO (Numerically Controlled Oscillator): Phase Accumulator
- Near-Memory Processing for Bandwidth-Efficient Compute
- Near-Threshold Computing (NTC): Operation at ~VT
- Operand Isolation: Disable Switching Activity in Idle Logic
- Overflow Detection: XOR of Sign Bits Carries
- Parallel FFT for High-Throughput Applications
- Pipelined FFT: Single-Path Delay Feedback (SDF) Architecture
- Pipelined Multiplier: Throughput vs. Latency Design
- Polar Code Successive Cancellation Decoder Hardware
- Power Domain Partitioning: Always-On and Switchable Domains
- Power Estimation in Early RTL Phase: Activity Propagation
- Power Gating: MTCMOS Header / Footer Cell Design
- Power Intent Simulation: Cadence Voltus, Synopsys PrimePower
- Prefix Adders: Kogge-Stone for Minimum Depth
- Q-Format Arithmetic: Overflow, Saturation, Rounding
- Reed-Solomon Decoder: Berlekamp-Massey Algorithm
- Retention Flip-Flop: Balloon Latch for State Preservation
- Ripple Carry Adder vs. Prefix Adder: Area-Delay Trade-off
- SRT Division Algorithm (Radix-2, Radix-4)
- Short-Circuit Power: Crowbar Current During Switching
- Signed Addition and Subtraction in Two's Complement
- Sources of Power in CMOS: Dynamic, Short-Circuit, Leakage
- Stochastic Computing: Probabilistic Logic Circuits
- Sub-Threshold Logic Design: Stability and Speed Trade-offs
- Subthreshold Leakage: Exponential Dependency on VT
- Supply Voltage Noise and On-Chip Decap Strategy
- Turbo Decoder MAP: Log-BCJR Algorithm in Hardware
- UPF (Unified Power Format): Power Intent Specification
- Ultra-Low-Power MCU Design: Duty Cycle, RTC Wake-Up
- Viterbi Decoder: ACS (Add-Compare-Select) Hardware
- Wallace Tree and Dadda Tree Multiplier Structures
Staff Engineer· 40
- AI-Assisted EDA: ML for Placement, Routing, Timing Prediction
- Boundary Scan (JTAG IEEE 1149.1) Integration
- Clock Domain Crossing (CDC) Formal Verification
- Clock Tree Synthesis (CTS): H-Tree, Balance, Useful Skew
- DFM (Design for Manufacturability): Density, Via Rules
- DRC (Design Rule Check) and LVS (Layout vs. Schematic)
- Design Specification: Micro-Architecture and Block Diagram
- ECO (Engineering Change Order): Timing and Functional Fixes
- Electromigration Sign-off: Current Density Checks
- Fault Models: Stuck-At, Transition, Path-Delay
- Floorplanning: Die Size, Aspect Ratio, Macro Placement
- Formal Equivalence Checking (LEC): Conformal / Formality
- Formal Property Verification: JasperGold, VC Formal
- Functional Simulation: VCS, ModelSim, Questa Simulator
- IR Drop Sign-off: Voltus / RedHawk Analysis
- Liberty (.lib) Timing Model: Cell Delay, Slew, Capacitance
- Logic Synthesis QoR: Area, Power, Timing Trade-off
- Logic Synthesis: Synopsys Design Compiler / Cadence Genus
- Multi-Corner Multi-Mode (MCMM) Timing Analysis
- On-Chip Variation (OCV): Derate Factors, AOCV, POCV
- Open-Source EDA: OpenROAD, OpenLane, Sky130 PDK
- Parasitic Extraction: RC Extraction with StarRC / Quantus
- Physical Verification: Calibre DRC, LVS, ERC
- Placement: Timing-Driven, Congestion-Aware Placement
- Post-Layout STA with Extracted Parasitics
- Post-Silicon Validation: Bring-Up, JTAG Debugging
- Power Planning: Power Rings, Straps, IR Drop Target
- RTL Design Entry and Linting (SpyGlass / Jasper)
- RTL-to-GDS Flow Overview: Synthesis, PnR, Signoff
- Routing: Global Routing, Detailed Routing, Via Optimization
- STA Concepts: Setup Slack, Hold Slack, Timing Paths
- Scan Compression (XTOL, EDT): Test Data Volume Reduction
- Scan Insertion: DFT Compiler, ATPG Flow Overview
- Signal Integrity (SI): Crosstalk Analysis and Fixing
- Silicon Debug: Scan Chain, Logic Analyzer, Scope
- Static Timing Analysis (STA): PrimeTime / Tempus
- Synthesis Constraints (SDC): Clock, Input/Output Delays
- Tapeout Checklist: GDS-II Merge, Seal Ring, Antenna Check
- Technology File (LEF / DEF) and PDK Usage
- Technology Library: Standard Cell, IO Cell, Macro
Distinguished Engineer· 40
- ATPG: Pattern Generation, Fault Simulation, Coverage Report
- Assume-Guarantee Reasoning in Formal Verification
- At-Speed Test: Transition Fault and Timing-Aware ATPG
- Automotive IC Qualification: ISO 26262 Verification Evidence
- Bug Tracking and Root Cause Analysis in Verification
- CDC Formal Verification: Clock Domain Analysis
- Clock and Reset Generation in Testbench
- Code Coverage: Statement, Branch, Toggle Coverage
- Constrained Random Verification (CRV): Stimulus Generation
- Coverage-Driven Verification (CDV) Methodology
- Emulation Platforms: Cadence Palladium, Synopsys ZeBu
- FPGA Prototype for Pre-Silicon Software Bring-Up
- Formal Apps: Datapath Verification, CDC, RDC Sign-off
- Formal Equivalence Checking: Combinational and Sequential
- Formal Property Checking: Bounded Model Checking (BMC)
- Functional Coverage: Covergroup, Coverpoint, Cross
- Hardware-Software Co-Verification: Arm Fast Models
- Mixed-Signal Verification: AMS (Analog-Mixed-Signal)
- Mutation Testing: Injecting Logic Faults to Qualify Tests
- Post-Silicon Validation: ATE (Automatic Test Equipment)
- Random Seed Management and Reproducibility
- Regression Management: Regression Suite, Nightly Runs
- SVA Properties: always, eventually, until
- SVA Sequences: ##, [*], [->], [=] Temporal Operators
- Self-Checking Testbench: Golden Reference Comparison
- Simulation-Based Verification: Directed and Random Tests
- SystemVerilog Assertions (SVA): Immediate and Concurrent
- Testbench Architecture: DUT, Driver, Monitor, Checker
- Transaction-Level Modeling (TLM) and TLM-2.0
- UVM (Universal Verification Methodology) Architecture
- UVM Agent: Sequencer, Driver, Monitor Components
- UVM Configuration Database (uvm_config_db)
- UVM Factory: Override and Extension Mechanism
- UVM Phases: Build, Connect, Run, Wrap-Up
- UVM Register Model (RAL): Register Map and Frontdoor Access
- UVM Scoreboard and Predictor Design
- UVM Sequences and Sequence Items
- Unbounded Proof: k-Induction and PDR/IC3 Methods
- Verification Goals: Correctness, Coverage, Completeness
- Verification IP (VIP): AXI, PCIe, USB, DDR VIP Usage