Digital Electronics
Logic design, combinational/sequential circuits, digital arithmetic, HDL design, and digital system architecture.
400 topics · 9 with articles
Intern Engineer· 2 of 80
- ASCII, Unicode, and Character Encoding StandardsArticle coming
- Arithmetic Shifts vs. Logical ShiftsArticle coming
- BCD (Binary-Coded Decimal): Packed and UnpackedArticle coming
- BCD Adder: Sum Correction for BCD OutputArticle coming
- Barrel Shifter Operation and ApplicationsArticle coming
- Barrel Shifter: Combinational Shift by N BitsRead
- Binary Division: Restoring and Non-Restoring MethodsArticle coming
- Binary Multiplication: Partial Products MethodArticle coming
- Binary Number System: Bit, Byte, Word, MSB, LSBArticle coming
- Binary-to-Hex and Hex-to-Binary ShortcutsArticle coming
- Bitwise Operations: Masking, Setting, Clearing, TogglingArticle coming
- Boolean Algebra: AND, OR, NOT, NAND, NOR, XOR, XNORArticle coming
- Boolean Identities and Theorems (De Morgan's Laws)Article coming
- Booth's Algorithm for Signed MultiplicationArticle coming
- CMOS Logic: Fan-Out, Noise Margin, Power DissipationArticle coming
- CMOS Transmission Gate: Pass Transistor LogicArticle coming
- Canonical POS (Product of Sums) FormArticle coming
- Canonical SOP (Sum of Products) FormArticle coming
- Carry Look-Ahead Adder (CLA): Group Propagate and GenerateArticle coming
- Carry-Ripple vs. Carry-Look-Ahead Trade-offArticle coming
- Carry-Save Adder (CSA) for Multiplier TreesArticle coming
- Combinational Logic Power: Cv²f and Short-Circuit PowerArticle coming
- Comparator: 1-bit, 4-bit Magnitude ComparisonArticle coming
- Critical Path Analysis in Combinational CircuitsArticle coming
- Crossbar Switch (Permutation Network) ArchitectureArticle coming
- Cyclic Redundancy Check (CRC) Polynomial DivisionArticle coming
- Decimal to Binary Conversion and Vice VersaArticle coming
- Decoder: 2-to-4, 3-to-8 Active-High and Active-LowArticle coming
- Demultiplexer (DEMUX): 1:2, 1:4, 1:8 Decoder FunctionArticle coming
- Duality Principle in Boolean AlgebraArticle coming
- Encoder: Priority Encoder (4-to-2, 8-to-3)Article coming
- Error-Correcting Codes (ECC): Hamming Distance ConceptArticle coming
- Excess-3 (XS-3) Code for BCD ArithmeticArticle coming
- Fixed-Point Number Representation: Q-Format (Qm.n)Article coming
- Floating-Point Rounding Modes (Round-to-Nearest, Truncate)Article coming
- Full Adder: Sum, Carry-In, and Carry-OutArticle coming
- Gate-Level Schematic: Symbols and Truth TablesArticle coming
- Glitch Power in Combinational Logic and MitigationArticle coming
- Gray Code: Definition, Encoding, and ApplicationsArticle coming
- Half Adder: Sum and Carry LogicArticle coming
- Hamming Code: Error Detection and Correction BasicsArticle coming
- Hazard Elimination: Redundant Gate TechniqueArticle coming
- Hazards in Combinational Logic: Static-0, Static-1, DynamicArticle coming
- IEEE 754 Floating-Point: Single and Double PrecisionArticle coming
- IEEE 754 Special Values: NaN, Infinity, DenormalsArticle coming
- Integer Division: Array Divider and SRT AlgorithmArticle coming
- K-Map: Grouping Rules, Don't-Care ConditionsArticle coming
- Karnaugh Map (K-Map): 2, 3, 4, 5-Variable SimplificationArticle coming
- Logic Families: CMOS, TTL, ECL, and Key ParametersArticle coming
- Logic Function Minimization for Cost and SpeedArticle coming
- Logic Gates: AND, OR, NOT, NAND, NOR, XOR, XNORArticle coming
- Logic Levels: VIL, VIH, VOL, VOH and Noise MarginsRead
- MUX-Based Function Generator: Any Boolean FunctionArticle coming
- Minterm and Maxterm NotationArticle coming
- Multiplexer (MUX): 2:1, 4:1, 8:1 and Enable ControlArticle coming
- Number System Conversion Table Quick ReferenceArticle coming
- Octal and Hexadecimal Number SystemsArticle coming
- One's Complement: Definition and SubtractionArticle coming
- Ones-Count / Population Count (Popcount) OperationArticle coming
- Overflow and Underflow in Fixed-Width ArithmeticArticle coming
- Parallel Prefix Adder: Kogge-Stone, Brent-Kung, Han-CarlsonArticle coming
- Parity Bit: Even and Odd Parity GenerationArticle coming
- Positive vs. Negative Logic ConventionArticle coming
- Priority Encoder Application: Interrupt ControllerArticle coming
- Programmable Logic Array (PLA) and PALArticle coming
- Propagation Delay (tpd), Contamination Delay (tcd)Article coming
- Quine-McCluskey (Tabular) Minimization MethodArticle coming
- ROM as Combinational Logic LUT ImplementationArticle coming
- Ripple Carry Adder (RCA): Propagation Delay AnalysisArticle coming
- Shannon's Expansion TheoremArticle coming
- Signed Integer Representation: Sign-MagnitudeArticle coming
- Standard Cell Library: Drive Strength and Delay ModelingArticle coming
- Subtractor: Half and Full Subtractor Using ComplementArticle coming
- Technology Mapping: NAND2/INV Gate ImplementationArticle coming
- Tri-State (Three-State) Buffer and Bus ArchitectureArticle coming
- Two's Complement: Representation and ArithmeticArticle coming
- Universal Gates: NAND-Only and NOR-Only ImplementationsArticle coming
- Wallace Tree Multiplier ArchitectureArticle coming
- Wired Logic and Open-Drain / Open-Collector GatesArticle coming
- Wired-AND and Wired-OR (Open-Collector) LogicArticle coming
Junior Engineer· 1 of 40
- Asynchronous FIFO: Write Pointer, Read Pointer, Empty/FullArticle coming
- BCD Counter (Decade Counter): 0–9 SequenceArticle coming
- Clock Domain Crossing (CDC): FIFO, Handshake, Bus EncodingArticle coming
- Clock Gating for Sequential Power ReductionArticle coming
- Clock Jitter: Cycle-to-Cycle and Long-Term AccumulatedArticle coming
- Clock Skew and Its Effect on Setup and Hold MarginsArticle coming
- Counter Design: Ripple (Asynchronous) CounterArticle coming
- D Flip-Flop: Rising-Edge Triggered, Timing ParametersArticle coming
- D Latch: Transparent and Opaque OperationArticle coming
- FSM Design: State Diagram, State Table, Next-State LogicArticle coming
- FSM Optimization: State Minimization (Implication Table)Article coming
- FSM State Encoding: Binary, One-Hot, Gray CodeArticle coming
- Finite State Machine (FSM): Mealy vs. Moore ArchitectureArticle coming
- Gray-Code Encoded FIFO for CDCArticle coming
- Hold Time Constraint: tckq + tcd ≥ thArticle coming
- JK Flip-Flop: Truth Table and Toggle ModeArticle coming
- LFSR Maximal-Length Sequence (m-Sequence) PropertiesArticle coming
- Latches vs. Flip-Flops: Level-Sensitive vs. Edge-TriggeredArticle coming
- Linear Feedback Shift Register (LFSR): Polynomial TapsArticle coming
- Low-Power State Retention Flip-Flop with Balloon LatchArticle coming
- Memory Element Comparison: SRAM Cell vs. DRAM CellArticle coming
- Metastability: MTBF Calculation and Synchronizer DesignArticle coming
- Modulo-N Counter: Synchronous and Asynchronous ResetArticle coming
- Pipeline Register Insertion for RetimingArticle coming
- Power in Sequential Logic: Clock Tree, Flip-Flop SwitchingArticle coming
- Register File: Read and Write Port ArchitectureArticle coming
- Retiming: Moving Registers Across Combinational LogicArticle coming
- Ring Counter and Johnson (Twisted-Ring) CounterArticle coming
- SR Latch: NAND and NOR Implementations, Forbidden StateArticle coming
- Setup Time (tsu), Hold Time (th), Clock-to-Q Delay (tckq)Article coming
- Shift Register Applications: Serial-to-Parallel ConversionArticle coming
- Shift Register: Serial-In Serial-Out (SISO), SIPO, PISO, PIPORead
- Synchronizer Design: Double-Register (2-FF) SynchronizerArticle coming
- Synchronous Down-Counter and Up-Down CounterArticle coming
- Synchronous FIFO: Depth Calculation, Status FlagsArticle coming
- Synchronous Reset vs. Asynchronous Reset Flip-FlopArticle coming
- Synchronous Up-Counter: D-FF and Combinational LogicArticle coming
- T Flip-Flop: Toggle Operation and Counter ApplicationArticle coming
- Timing Analysis: False Paths and Multicycle PathsArticle coming
- Timing Constraints: Setup Slack = Tclock - tckq - tpd - tsuArticle coming
Middle Engineer· 1 of 120
- 3D NAND Flash: Vertical Channel, Layer Count (128+)Article coming
- AXI4-Lite Protocol RTL: Ready/Valid HandshakeArticle coming
- AXI4-Stream RTL: TDATA, TVALID, TREADY, TLASTArticle coming
- Arbiter RTL Design: Round-Robin, PriorityArticle coming
- BRAM Inference vs. Instantiation Trade-offsArticle coming
- Block RAM (BRAM): True Dual-Port, Simple Dual-Port, SDPArticle coming
- Blocking (=) vs. Non-Blocking (<=) Assignment RulesArticle coming
- Cache Coherence Protocols: MESI, MOESI, MESIFArticle coming
- Cache Memory Architecture: Direct-Mapped, Set-Associative, Fully-AssociativeArticle coming
- Cache Replacement Policies: LRU, LFU, FIFO, RandomArticle coming
- Catapult HLS / Vivado HLS Directives and PragmasArticle coming
- Chip-Level Power Estimation: XPower, Intel PowerPlayArticle coming
- ChipScope / Signal Tap / Reveal: In-System DebugArticle coming
- Clock Gating RTL: ICG Cell and Enable FlopArticle coming
- Constraint File (SDC): create_clock, set_input_delayArticle coming
- Constraint-Driven Design: XDC and QSF Constraint FilesArticle coming
- Content-Addressable Memory (CAM): TCAM for Routing TablesArticle coming
- Continuous Assignment (assign): Combinational ModelingArticle coming
- DDR4 SDRAM: Differential Clock, Data Strobe (DQS), ODTArticle coming
- DDR5: Inline ECC, Decision Feedback Equalization (DFE)Article coming
- DRAM Addressing: Row Address Strobe (RAS) and CASArticle coming
- DRAM Cell: 1T1C Structure, Capacitor Charge RetentionArticle coming
- DRAM Refresh: tREF, tRFC, Distributed vs. Burst RefreshArticle coming
- DSP Slice Cascading for High-Precision ArithmeticArticle coming
- DSP48 / DSP Slice: Multiply-Accumulate (MAC) OperationArticle coming
- Distributed RAM: LUT-Based RAM in SliceArticle coming
- ECC DRAM: SECDED, Chipkill CorrectionArticle coming
- EEPROM: Byte-Erasable, Endurance, Data Retention SpecsArticle coming
- Emerging NVM: MRAM (Magnetoresistive RAM) PropertiesArticle coming
- FIFO Generator IP: Common Clock and Independent ClockArticle coming
- FIFO RTL Design: Pointer Arithmetic, FlagsArticle coming
- FPGA Anti-Tamper and Configuration SecurityArticle coming
- FPGA Architecture: LUT, Flip-Flop, BRAM, DSP, IO BlocksArticle coming
- FPGA Clock Resources: MMCM, PLL, Global/Regional BuffersArticle coming
- FPGA Configuration: JTAG, SPI Flash, SelectMAP, USBArticle coming
- FPGA I/O Standards: LVCMOS, LVDS, HSTL, SSTLArticle coming
- FPGA Machine Learning Inference: Vitis AI, hls4mlArticle coming
- FPGA Place and Route: Floorplanning, Pipelining for FmaxArticle coming
- FPGA Power Optimization: Logic, Routing, I/O, StaticArticle coming
- FPGA Prototyping of ASIC / SoC DesignsArticle coming
- FPGA Routing: Switch Matrix, Connection Boxes, Routing ChannelsArticle coming
- FPGA Security: Bitstream Encryption and AuthenticationArticle coming
- FPGA Soft-Core Processors: MicroBlaze, NIOS II, RISC-VArticle coming
- FSM Coding in Verilog: One-Hot, Binary, Two-Process StyleArticle coming
- FeRAM (Ferroelectric RAM): Polarization SwitchingArticle coming
- Flash Controller: FTL (Flash Translation Layer) DesignArticle coming
- Flash ECC: BCH, LDPC for Error CorrectionArticle coming
- Flash Wear Leveling: Static, Dynamic, Global AlgorithmsArticle coming
- For-Generate and If-Generate ConstructsArticle coming
- GDDR6: Graphics Memory Bandwidth and PAM4 SignalingArticle coming
- HBM (High Bandwidth Memory): Silicon Interposer, TSVArticle coming
- HLS IP Integration in Vivado / QuartusArticle coming
- Hierarchical Design: Module Instantiation, Port MappingArticle coming
- High-Level Design: OpenCL on FPGA (Intel oneAPI, Vitis HLS)Article coming
- High-Level Synthesis (HLS): C++ to RTL Flow OverviewArticle coming
- High-Speed Transceiver (GTX, GTP, GTH): SerDes BasicsArticle coming
- Intel Agilex: Heterogeneous Tiles and HBM IntegrationArticle coming
- Intel Quartus Prime: Compilation, Timing AnalysisArticle coming
- JTAG AXI Master: On-Chip Debug Without External ProbeArticle coming
- LPDDR5: Low-Power DRAM for Mobile and WearableArticle coming
- Lattice Diamond and Radiant Tools OverviewArticle coming
- Look-Up Table (LUT): N-Input Function ImplementationArticle coming
- MRAM STT-MRAM: Write Energy and Read DisturbArticle coming
- Memory Bandwidth and Latency Trade-offsArticle coming
- Memory Controller in FPGA: DDR4/LPDDR4 MIG IPArticle coming
- Memory Hierarchy: L1, L2, L3 Cache and Main MemoryArticle coming
- Multi-FPGA Partitioning and Inter-FPGA InterfaceArticle coming
- NAND Flash: Page, Block, Plane Hierarchy and Erase CycleArticle coming
- NOR Flash Memory: Random Access, Execute-in-Place (XIP)Article coming
- NVMe Protocol over PCIe: Command Queue and Low LatencyArticle coming
- Named vs. Positional Port ConnectionArticle coming
- Open-Source FPGA Toolchain: Yosys, nextpnr, OpenFPGAArticle coming
- PCIe Hard IP Core in FPGA: Endpoint ConfigurationArticle coming
- Parameterized Modules and VHDL GenericsArticle coming
- Partial Reconfiguration (PR): Dynamic Region DesignArticle coming
- Phase Change Memory (PCM / 3D XPoint): Set/ResetArticle coming
- Pipeline RTL Design: Stall, Flush, Hazard HandlingArticle coming
- Procedural Blocks: always @(*) for Combinational LogicArticle coming
- Processing in Memory (PIM / PNM): Computational StorageArticle coming
- ROM Types: Mask ROM, OTP PROM, EPROM, EEPROMArticle coming
- RRAM / Memristor: Resistive Switching MechanismArticle coming
- RTL Coding Guidelines: Reset Strategy, Coding StyleArticle coming
- RTL Linting: Common Warnings and Error ClassesArticle coming
- RTL for Memories: Synchronous Read, Write EnableArticle coming
- SDC: set_false_path, set_multicycle_path, set_max_delayArticle coming
- SDRAM: Synchronous Operation, Burst Mode, Bank ArchitectureArticle coming
- SLC, MLC, TLC, QLC NAND: Bits-per-Cell Trade-offsArticle coming
- SRAM Cell: 6-Transistor (6T) Structure and OperationArticle coming
- SRAM Read Operation: Bit-Line Precharge and Sense AmplifierArticle coming
- SRAM Speed vs. Area Trade-off: Cell SizingArticle coming
- SRAM Stability: Static Noise Margin (SNM) Butterfly CurveArticle coming
- SRAM Write Operation: Write Driver and Word LineArticle coming
- SRAM vs. DRAM vs. Flash vs. NVM Comparison MatrixArticle coming
- Scratchpad Memory in Embedded ProcessorsArticle coming
- Sequential Procedural Block: always @(posedge clk)Article coming
- Simulation Delta Cycle and Event-Driven SemanticsArticle coming
- Synthesis-Friendly RTL: Inferred Latches, Unintended LoopsArticle coming
- SystemVerilog Data Types: logic, bit, int, shortrealArticle coming
- SystemVerilog Interfaces and ModportArticle coming
- SystemVerilog Packages and TypedefArticle coming
- Timing Closure: Critical Path, Register RetimingRead
- VHDL 2008 and SystemVerilog 2012 Key EnhancementsArticle coming
- VHDL Data Types: std_logic, std_logic_vector, unsigned, signedArticle coming
- VHDL Entity and Architecture: Signal, Variable, ConstantArticle coming
- VHDL Process Statement: Sensitivity List and WaitArticle coming
- VHDL if-elsif-else and case StatementArticle coming
- Verilog Data Types: wire, reg, integer, real, timeArticle coming
- Verilog Module Declaration: port, wire, reg, parameterArticle coming
- Verilog Operators: Arithmetic, Logical, Bitwise, ReductionArticle coming
- Verilog Packages and VHDL Package / Library UseArticle coming
- Verilog Testbench Structure: DUT, Clock Gen, StimulusArticle coming
- Verilog if-else and case / casex / casez StatementsArticle coming
- Verilog vs. VHDL: Language Philosophy and Key DifferencesArticle coming
- Version Control for RTL: Git Workflow and ReviewArticle coming
- Xilinx CLB / Altera (Intel) ALM ArchitectureArticle coming
- Xilinx Vivado Design Suite: Project and IP FlowArticle coming
- Xilinx Zynq: PS (ARM) and PL (FPGA) IntegrationArticle coming
- Zynq UltraScale+ MPSoC: Quad-Core ARM + FPGAArticle coming
- eFPGA Embedded in SoC: Fabric Integration ChallengesArticle coming
- eMMC and UFS: Embedded Flash Storage InterfacesArticle coming
Senior Engineer· 4 of 80
- AI Inference Accelerator: MAC Array and Data FlowArticle coming
- Activity-Driven Power Analysis: Switching Activity Files (SAIF)Article coming
- Adaptive Voltage Scaling (AVS): Body Bias and Voltage TuneArticle coming
- Adiabatic Logic: Energy-Recovering Switching TechniqueArticle coming
- Approximate Computing: Bit-Width Truncation, Voltage ScalingArticle coming
- Array Multiplier: Partial Product Generation and SummationArticle coming
- Asynchronous (Clockless) Logic: Handshake ProtocolsArticle coming
- Binary Addition: Half Adder, Full Adder, Carry PropagationArticle coming
- Body Biasing: Forward Body Bias (FBB) and RBB for LeakageRead
- Booth's Algorithm: Radix-2 Signed MultiplicationArticle coming
- CIC (Cascaded Integrator-Comb) Filter HardwareArticle coming
- CORDIC Algorithm: Rotation Mode for Sin, Cos, ArctanArticle coming
- CORDIC Vectoring Mode: Magnitude and Phase ComputationArticle coming
- CPF (Common Power Format): Alternative Power SpecArticle coming
- Carry Look-Ahead Adder (CLA): G and P TermsArticle coming
- Clock Gating: Integrated Clock Gate (ICG) Cell UsageArticle coming
- DDS (Direct Digital Synthesis): Spurious PerformanceArticle coming
- Data Gating: Suppressing Transitions in Unused Data PathsArticle coming
- Digital Mixer: I/Q Downconversion and UpconversionArticle coming
- Dynamic Power: P = α C V² f (Activity, Cap, Voltage, Freq)Read
- Dynamic Voltage and Frequency Scaling (DVFS)Article coming
- Electromigration (EM): Current Density Limits in MetalArticle coming
- Energy-Quality Scaling in Deep Learning AcceleratorsArticle coming
- FFT Hardware Architecture: Radix-2 Butterfly UnitsArticle coming
- FIR Filter Direct-Form Hardware ImplementationArticle coming
- FIR Filter Polyphase Decomposition for DownsamplingArticle coming
- FIR Filter Transposed-Form for Reduced Critical PathArticle coming
- Fixed-Point DSP: Quantization Error and Dynamic RangeArticle coming
- Floating-Point Addition: Alignment, Addition, NormalizationArticle coming
- Floating-Point Division: Newton-Raphson IterationArticle coming
- Floating-Point Multiplication: Mantissa Multiply, Exp AddArticle coming
- Gate Leakage: Quantum Tunneling Through Thin Gate OxideArticle coming
- Globally Asynchronous Locally Synchronous (GALS) DesignArticle coming
- Half-Band FIR Filter: Efficient Decimation by 2Article coming
- High-Vt Cells for Leakage Reduction in Non-Critical PathsArticle coming
- IFFT for OFDM Symbol GenerationArticle coming
- IIR Biquad Section (SOS) for Cascade ImplementationArticle coming
- IIR Filter: Direct Form I and II Hardware RealizationArticle coming
- IR Drop Analysis: Static (STA-Based) and Dynamic (Transient)Article coming
- Integer Division: Restoring and Non-Restoring AlgorithmArticle coming
- Isolation Cell: Clamping Power Domain Outputs to Logic LevelArticle coming
- Junction Leakage: Reverse-Biased Diode CurrentRead
- LDPC Decoder: Check Node and Variable Node ProcessingArticle coming
- Level Shifter: Low-to-High and High-to-Low ConversionArticle coming
- Long-Channel Devices for Ultra-Low LeakageArticle coming
- Low-Power Memory: SRAM with Dual-Rail, Assist TechniquesArticle coming
- Mobile SoC Power Management: PMIC Collaboration, DVFS ProfilesArticle coming
- Modified Booth Encoding: Radix-4 for Faster MultiplyArticle coming
- Multi-Vt (Threshold Voltage) Cell Library StrategyArticle coming
- NCO (Numerically Controlled Oscillator): Phase AccumulatorArticle coming
- Near-Memory Processing for Bandwidth-Efficient ComputeArticle coming
- Near-Threshold Computing (NTC): Operation at ~VTArticle coming
- Operand Isolation: Disable Switching Activity in Idle LogicArticle coming
- Overflow Detection: XOR of Sign Bits CarriesArticle coming
- Parallel FFT for High-Throughput ApplicationsArticle coming
- Pipelined FFT: Single-Path Delay Feedback (SDF) ArchitectureArticle coming
- Pipelined Multiplier: Throughput vs. Latency DesignArticle coming
- Polar Code Successive Cancellation Decoder HardwareArticle coming
- Power Domain Partitioning: Always-On and Switchable DomainsArticle coming
- Power Estimation in Early RTL Phase: Activity PropagationArticle coming
- Power Gating: MTCMOS Header / Footer Cell DesignArticle coming
- Power Intent Simulation: Cadence Voltus, Synopsys PrimePowerArticle coming
- Prefix Adders: Kogge-Stone for Minimum DepthArticle coming
- Q-Format Arithmetic: Overflow, Saturation, RoundingArticle coming
- Reed-Solomon Decoder: Berlekamp-Massey AlgorithmArticle coming
- Retention Flip-Flop: Balloon Latch for State PreservationArticle coming
- Ripple Carry Adder vs. Prefix Adder: Area-Delay Trade-offArticle coming
- SRT Division Algorithm (Radix-2, Radix-4)Article coming
- Short-Circuit Power: Crowbar Current During SwitchingArticle coming
- Signed Addition and Subtraction in Two's ComplementArticle coming
- Sources of Power in CMOS: Dynamic, Short-Circuit, LeakageArticle coming
- Stochastic Computing: Probabilistic Logic CircuitsArticle coming
- Sub-Threshold Logic Design: Stability and Speed Trade-offsArticle coming
- Subthreshold Leakage: Exponential Dependency on VTRead
- Supply Voltage Noise and On-Chip Decap StrategyArticle coming
- Turbo Decoder MAP: Log-BCJR Algorithm in HardwareArticle coming
- UPF (Unified Power Format): Power Intent SpecificationArticle coming
- Ultra-Low-Power MCU Design: Duty Cycle, RTC Wake-UpArticle coming
- Viterbi Decoder: ACS (Add-Compare-Select) HardwareArticle coming
- Wallace Tree and Dadda Tree Multiplier StructuresArticle coming
Staff Engineer· 1 of 40
- AI-Assisted EDA: ML for Placement, Routing, Timing PredictionArticle coming
- Boundary Scan (JTAG IEEE 1149.1) IntegrationArticle coming
- Clock Domain Crossing (CDC) Formal VerificationArticle coming
- Clock Tree Synthesis (CTS): H-Tree, Balance, Useful SkewArticle coming
- DFM (Design for Manufacturability): Density, Via RulesArticle coming
- DRC (Design Rule Check) and LVS (Layout vs. Schematic)Article coming
- Design Specification: Micro-Architecture and Block DiagramArticle coming
- ECO (Engineering Change Order): Timing and Functional FixesArticle coming
- Electromigration Sign-off: Current Density ChecksArticle coming
- Fault Models: Stuck-At, Transition, Path-DelayArticle coming
- Floorplanning: Die Size, Aspect Ratio, Macro PlacementArticle coming
- Formal Equivalence Checking (LEC): Conformal / FormalityArticle coming
- Formal Property Verification: JasperGold, VC FormalArticle coming
- Functional Simulation: VCS, ModelSim, Questa SimulatorArticle coming
- IR Drop Sign-off: Voltus / RedHawk AnalysisArticle coming
- Liberty (.lib) Timing Model: Cell Delay, Slew, CapacitanceArticle coming
- Logic Synthesis QoR: Area, Power, Timing Trade-offArticle coming
- Logic Synthesis: Synopsys Design Compiler / Cadence GenusArticle coming
- Multi-Corner Multi-Mode (MCMM) Timing AnalysisArticle coming
- On-Chip Variation (OCV): Derate Factors, AOCV, POCVArticle coming
- Open-Source EDA: OpenROAD, OpenLane, Sky130 PDKArticle coming
- Parasitic Extraction: RC Extraction with StarRC / QuantusArticle coming
- Physical Verification: Calibre DRC, LVS, ERCArticle coming
- Placement: Timing-Driven, Congestion-Aware PlacementArticle coming
- Post-Layout STA with Extracted ParasiticsArticle coming
- Post-Silicon Validation: Bring-Up, JTAG DebuggingArticle coming
- Power Planning: Power Rings, Straps, IR Drop TargetArticle coming
- RTL Design Entry and Linting (SpyGlass / Jasper)Article coming
- RTL-to-GDS Flow Overview: Synthesis, PnR, SignoffArticle coming
- Routing: Global Routing, Detailed Routing, Via OptimizationArticle coming
- STA Concepts: Setup Slack, Hold Slack, Timing PathsArticle coming
- Scan Compression (XTOL, EDT): Test Data Volume ReductionArticle coming
- Scan Insertion: DFT Compiler, ATPG Flow OverviewArticle coming
- Signal Integrity (SI): Crosstalk Analysis and FixingArticle coming
- Silicon Debug: Scan Chain, Logic Analyzer, ScopeArticle coming
- Static Timing Analysis (STA): PrimeTime / TempusRead
- Synthesis Constraints (SDC): Clock, Input/Output DelaysArticle coming
- Tapeout Checklist: GDS-II Merge, Seal Ring, Antenna CheckArticle coming
- Technology File (LEF / DEF) and PDK UsageArticle coming
- Technology Library: Standard Cell, IO Cell, MacroArticle coming
Distinguished Engineer· 0 of 40
- ATPG: Pattern Generation, Fault Simulation, Coverage ReportArticle coming
- Assume-Guarantee Reasoning in Formal VerificationArticle coming
- At-Speed Test: Transition Fault and Timing-Aware ATPGArticle coming
- Automotive IC Qualification: ISO 26262 Verification EvidenceArticle coming
- Bug Tracking and Root Cause Analysis in VerificationArticle coming
- CDC Formal Verification: Clock Domain AnalysisArticle coming
- Clock and Reset Generation in TestbenchArticle coming
- Code Coverage: Statement, Branch, Toggle CoverageArticle coming
- Constrained Random Verification (CRV): Stimulus GenerationArticle coming
- Coverage-Driven Verification (CDV) MethodologyArticle coming
- Emulation Platforms: Cadence Palladium, Synopsys ZeBuArticle coming
- FPGA Prototype for Pre-Silicon Software Bring-UpArticle coming
- Formal Apps: Datapath Verification, CDC, RDC Sign-offArticle coming
- Formal Equivalence Checking: Combinational and SequentialArticle coming
- Formal Property Checking: Bounded Model Checking (BMC)Article coming
- Functional Coverage: Covergroup, Coverpoint, CrossArticle coming
- Hardware-Software Co-Verification: Arm Fast ModelsArticle coming
- Mixed-Signal Verification: AMS (Analog-Mixed-Signal)Article coming
- Mutation Testing: Injecting Logic Faults to Qualify TestsArticle coming
- Post-Silicon Validation: ATE (Automatic Test Equipment)Article coming
- Random Seed Management and ReproducibilityArticle coming
- Regression Management: Regression Suite, Nightly RunsArticle coming
- SVA Properties: always, eventually, untilArticle coming
- SVA Sequences: ##, [*], [->], [=] Temporal OperatorsArticle coming
- Self-Checking Testbench: Golden Reference ComparisonArticle coming
- Simulation-Based Verification: Directed and Random TestsArticle coming
- SystemVerilog Assertions (SVA): Immediate and ConcurrentArticle coming
- Testbench Architecture: DUT, Driver, Monitor, CheckerArticle coming
- Transaction-Level Modeling (TLM) and TLM-2.0Article coming
- UVM (Universal Verification Methodology) ArchitectureArticle coming
- UVM Agent: Sequencer, Driver, Monitor ComponentsArticle coming
- UVM Configuration Database (uvm_config_db)Article coming
- UVM Factory: Override and Extension MechanismArticle coming
- UVM Phases: Build, Connect, Run, Wrap-UpArticle coming
- UVM Register Model (RAL): Register Map and Frontdoor AccessArticle coming
- UVM Scoreboard and Predictor DesignArticle coming
- UVM Sequences and Sequence ItemsArticle coming
- Unbounded Proof: k-Induction and PDR/IC3 MethodsArticle coming
- Verification Goals: Correctness, Coverage, CompletenessArticle coming
- Verification IP (VIP): AXI, PCIe, USB, DDR VIP UsageArticle coming