Subthreshold Leakage: Exponential Dependency on VT

What Is Subthreshold Leakage?

Definition and physical origin in MOS transistors

A MOSFET switched "off" does not actually stop conducting. Below the threshold voltage VT, the channel is in weak inversion — the surface potential is too low to form a strong inversion layer, but minority carrier concentration at the surface is still nonzero and varies exponentially with gate voltage. Carriers diffuse from source to drain the same way minority carriers diffuse across a forward-biased junction. This diffusion current, flowing even when VGS = 0, is subthreshold leakage. It is not a defect — it is the intrinsic behavior of a MOS device operating below its conduction threshold, and every transistor on your die contributes some amount of it whenever it is not actively switching.

Why it matters in modern nanometer-scale designs

In older processes (0.25 µm and above) subthreshold leakage was a rounding error next to dynamic power. As VDD and VT scaled down to keep switching power in check, the subthreshold slope did not shrink proportionally, so the off-state current climbed into the same order of magnitude as switching current. In a 7 nm or 5 nm design, leakage power can rival or exceed dynamic power in idle or lightly clocked blocks, and it is the dominant term in standby/retention modes. For battery-powered and thermally constrained designs, leakage is no longer a second-order correction — it is a first-class design target with its own sign-off flow.

Distinction from gate oxide and junction leakage

Subthreshold leakage is often lumped together with other off-state currents, but the mechanisms are different. Gate oxide (tunneling) leakage flows through the gate dielectric itself, driven by quantum mechanical tunneling and strongly dependent on oxide thickness — it is largely addressed by high-k/metal-gate stacks. Junction leakage flows across the reverse-biased source/drain-to-body diodes and is governed by the same physics covered in Reverse Bias: Leakage Current, Breakdown Mechanisms — minority carrier generation and diffusion in a reverse-biased pn junction. Subthreshold leakage, by contrast, is a channel conduction mechanism controlled by gate voltage relative to VT, not a diode effect, even though its exponential form looks similar to the diode equation you'd recognize from Forward Bias: Exponential Current, Knee Voltage. All three mechanisms are summed in a full leakage power budget, but they respond to different design levers, so conflating them leads to the wrong fix.

The Exponential Relationship: I_leak ∝ e^(-VT/nVT)

Derivation from weak-inversion carrier transport

In weak inversion, the MOSFET behaves like a bipolar transistor operating on diffusion current. The channel surface potential is set by the gate through a capacitive divider between the oxide capacitance and the depletion capacitance, and the carrier density at the source end of the channel falls off exponentially with the barrier height (VGS − VT). Integrating the diffusion current across the channel gives the standard subthreshold current equation:

I_sub = I_0 * (W/L) * exp( (VGS - VT) / (n * VT_thermal) ) * (1 - exp(-VDS / VT_thermal))

where VT_thermal = kT/q is the thermal voltage (~25.85 mV at 300 K), n is the subthreshold ideality factor, and I_0 bundles mobility, oxide capacitance, and geometry terms. At VGS = 0 this reduces to the familiar off-state leakage term that scales as exp(-VT / n*VT_thermal).

Role of the ideality factor (n) and thermal voltage

n (typically 1.2–1.5 for bulk CMOS, closer to 1.0–1.1 for fully-depleted SOI or FinFET devices) captures how much of the gate voltage swing is lost to the depletion capacitance divider instead of modulating the surface potential directly. A lower n means the gate has tighter electrostatic control over the channel — exactly what FinFETs and gate-all-around structures are built to deliver. The thermal voltage VT_thermal sets the scale of the exponential: at room temperature it is about 26 mV, so the "subthreshold swing" — the gate voltage change needed for a 10x change in current — works out to roughly 60 mV/decade at the ideal limit (n = 1), and 70–100 mV/decade in real bulk devices.

Why exponential, not linear scaling

The exponential form falls directly out of Boltzmann statistics: carrier concentration at an energy barrier scales as exp(-barrier/kT), not linearly with barrier height. VT acts as that barrier. There is no physical mechanism in weak inversion that would make leakage linear in VT — the carrier population itself is distributed exponentially in energy, and gate voltage shifts the barrier, not the population shape. This is the same mathematical structure as the forward-biased diode equation, which is why subthreshold leakage curves and diode I-V curves look alike on a log plot.

Practical implications of small VT shifts

Because of the exponential relationship, small VT shifts have outsized consequences. With a subthreshold swing of 70 mV/decade, a 70 mV reduction in VT multiplies leakage by 10x. A 50 mV reduction — well within the range of a corner shift or a temperature swing — multiplies leakage by roughly 10^(50/70) ≈ 5x to 6x, and in processes with tighter swing closer to 60 mV/decade, that same 50 mV drop can push leakage up by a factor of 7-8x. This is the core number every power architect should carry in their head: VT is not a knob you nudge gently, it is a knob you turn on a log scale.

Threshold Voltage Variation and Process Corners

Nominal, low-VT, and high-VT device corners

PDKs typically offer at least three VT flavors: standard-VT (SVT) for balanced performance, low-VT (LVT) for speed-critical paths at the cost of leakage, and high-VT (HVT) for leakage-sensitive, non-critical paths. Some advanced nodes add an ultra-low-VT (ULVT) option. Each flavor is a separate characterized library view, and swapping a cell from SVT to HVT can cut its leakage by an order of magnitude while adding meaningful delay.

Impact of manufacturing variability on leakage

VT itself is not a fixed number — it varies die-to-die and within-die due to random dopant fluctuation, line-edge roughness, and oxide thickness variation. A ±3σ VT spread of 30-50 mV is common at advanced nodes, and because leakage is exponential in VT, that spread translates into leakage variation of several times nominal across the distribution. This is why leakage sign-off is done at explicit process corners (e.g., fast-fast, slow-slow, and the leakage-specific "fast" corner where VT is at its statistical low end) rather than at a single typical value.

Temperature and supply voltage effects on VT

VT has a negative temperature coefficient — it drops by roughly 0.5-1.5 mV/°C depending on process, so a junction running at 125°C instead of 25°C can lose 50-100 mV of VT, which, combined with the exponential law above, can multiply subthreshold leakage several-fold. This is on top of the direct temperature dependence of VT_thermal itself, which also grows with absolute temperature and widens the subthreshold swing. VT also shifts with body bias and supply-dependent DIBL (drain-induced barrier lowering): higher VDS lowers the effective barrier at the drain end of the channel, increasing leakage further. These effects are the physical basis for deliberately manipulating VT through Body Biasing: Forward Body Bias (FBB) and RBB for Leakage, where reverse body bias raises the effective VT to suppress leakage in idle domains, and forward body bias trades leakage for speed when needed.

Worst-case leakage scenarios in design

Worst-case leakage sign-off combines the lowest VT corner, the highest operating temperature, and the highest supply voltage simultaneously — even if that combination is statistically unlikely for any single die, it bounds the thermal and battery budget you must design against. Skipping this combined corner is one of the most common causes of silicon that passes functional validation but fails thermal or battery-life specs in the field.

Measurement and Modeling in Design Tools

SPICE subthreshold current equations

Compact models (BSIM-CMG, BSIM4, PSP) implement the weak-inversion current with smoothing functions that blend it continuously into the strong-inversion drain current equation, so a transistor's I-V curve has no discontinuity at VT. Running a SPICE sweep of IDS vs. VGS at VDS = VDD with the device nominally "off" and plotting on a log axis is the standard way to extract subthreshold swing and off-state current directly from a given PDK's transistor models.

Characterization data in PDK liberty files

Standard-cell libraries characterize leakage current per cell, per input vector state, across supply voltage and temperature corners, and store it in .lib (Liberty) files as leakage power tables. Each cell has multiple leakage values depending on which inputs are high or low, because the number of stacked "off" transistors and their body effect differs by input pattern — a detail static power tools consume directly rather than re-deriving from device physics.

Static power analysis in commercial tools

Commercial power analysis tools (part of the same sign-off suites that run static timing analysis) read these Liberty leakage tables, apply the design's actual state probabilities or assume worst-case vectors, and sum leakage across the netlist at the chosen corner. This static power analysis loop runs in parallel with the timing closure flow and increasingly shares its corner definitions, since VT corners used for timing margin are the same corners used for leakage worst-casing.

Accuracy vs. simulation runtime trade-offs

Full SPICE-level leakage simulation of a multi-million-instance block is impractical; Liberty-based static analysis trades some accuracy (it does not capture every input transition or layout-dependent effect) for runtime that scales to full-chip size. Teams needing higher fidelity on a specific leakage-critical macro will fall back to SPICE or Monte Carlo variation analysis on that block alone, using the full-chip static result to identify which blocks deserve that extra scrutiny.

Design Strategies to Minimize Subthreshold Leakage

Circuit-level techniques: sleep transistors, stacking, and gating

Power gating inserts a high-VT sleep transistor between a logic block and its rail, cutting leakage by orders of magnitude when the block is idle, at the cost of wake-up latency and state retention complexity. Transistor stacking exploits the fact that two series "off" transistors leak less than one, because the internal node self-biases and reduces the effective VGS of the lower device — a free leakage reduction already present in many logic gates, and sometimes deliberately added in low-power cell variants. Clock and power gating at the RTL or architectural level reduce the fraction of the chip that is active, directly shrinking the leakage-contributing footprint.

Increasing VT through dopant concentration (trade-off with performance)

Raising VT via channel doping or work-function engineering is the most direct leakage lever, and it is exactly what HVT library cells do. The trade-off is drive current: higher VT means slower switching for the same VDD, so this technique is applied selectively rather than chip-wide.

Multi-VT library selection for critical paths

The standard flow assigns LVT cells only to paths that need the speed, SVT to the bulk of the design, and HVT everywhere timing slack allows. This VT assignment is typically automated by the place-and-route tool as a post-route leakage optimization step, swapping cell flavors on non-critical paths without touching logic function or placement.

Timing closure under leakage constraints

Because VT swaps affect delay, leakage optimization and timing closure are coupled — a tool that swaps too many cells to HVT in pursuit of a leakage target can blow timing margin on paths that looked non-critical at a different corner. Sign-off flows iterate leakage optimization and STA together, re-checking timing at the slow corner after every leakage-driven VT swap.

Integration with Power Management Techniques

Role in overall static power budgets

Total static power is the sum of subthreshold, gate, and junction leakage across every device on the die, scaled by however many domains are powered at a given time. In standby or deep-sleep modes, subthreshold leakage is usually the single largest term, which is why mobile and IoT power budgets are built around it rather than around active-mode dynamic power.

Interaction with dynamic power and frequency scaling

Dynamic power scales with CV²f as covered elsewhere, and the two power components pull in opposite directions during voltage scaling: lowering VDD to cut dynamic power pushes designers toward lowering VT to preserve speed margin, which directly inflates subthreshold leakage through the exponential relationship. DVFS (dynamic voltage and frequency scaling) schemes have to account for this coupling, since the leakage-optimal and dynamic-power-optimal VDD/VT points rarely coincide.

Leakage-aware placement and clock gating strategies

Placement tools increasingly consider leakage density alongside congestion and timing, clustering HVT cells in thermally hot regions to avoid compounding leakage with temperature-driven VT reduction. Clock gating, by stopping switching activity in idle blocks, indirectly helps leakage too: it is usually paired with power gating or body biasing so that the same idle logic that stops toggling also sees its effective VT raised, compounding the savings rather than leaving subthreshold current running unchecked in silence.