Junction Leakage: Reverse-Biased Diode Current

What is Junction Leakage?

Definition and physical origin in semiconductor junctions

Junction leakage is the small but persistent current that flows across a p-n junction when it is reverse-biased — the condition where, ideally, no current should flow at all. It originates at the interface between p-type and n-type silicon, where dopant atoms create a region depleted of free carriers. That depletion region is not a perfect insulator. It contains crystal defects, thermally generated carriers, and residual minority-carrier populations, all of which conspire to let a finite current sneak through even when the junction is "off."

In a digital IC, every source/drain diffusion sitting in a well forms a p-n junction with that well, and every well forms a junction with the substrate. At 28 nm and below, a chip can contain billions of these junctions, each contributing its own leakage path. Individually trivial, collectively they dominate standby power.

Why reverse bias creates leakage current

Apply a reverse bias and the depletion region widens, sweeping out free carriers and erecting a potential barrier that blocks the diffusion current responsible for forward conduction. In an ideal diode this barrier would reduce current to exactly zero. In a real diode, the applied field actively pulls minority carriers — electrons in the p-region, holes in the n-region — across the junction, and it also pulls out carriers generated by thermal processes inside the depletion region itself. The wider the depletion region, the more generation sites it contains, so reverse leakage tends to grow with reverse voltage, not stay flat as the simple exponential model implies.

Distinction between ideal and real diode behavior

The Shockley ideal diode equation predicts a reverse saturation current, I_S, that is constant and vanishingly small regardless of how large the reverse bias becomes. Real silicon diodes depart from this in three ways: generation current in the depletion region adds a term that scales with depletion width, surface leakage along passivation interfaces adds another path, and at sufficiently high field the junction approaches avalanche or tunneling breakdown. For the physics of avalanche multiplication and the breakdown knee itself, see Reverse Bias: Leakage Current, Breakdown Mechanisms. This article focuses on the leakage regime that exists well below breakdown — the regime every standby-power budget actually lives in.

Physics of Reverse Leakage Current

Generation-recombination current in the depletion region

Inside the depletion region, electron-hole pairs are continuously generated by thermal energy via trap states located in the silicon bandgap — defects, dislocations, and metallic contamination all introduce these states. Each generated pair is immediately separated by the junction's built-in field: the electron drifts to the n-side, the hole to the p-side, and both contribute to reverse current. This generation current, I_gen, is proportional to the depletion width W and the intrinsic carrier concentration n_i, and inversely proportional to the carrier lifetime τ in the depletion region. Because W grows with the square root of reverse voltage, I_gen grows too, more slowly than linearly but non-trivially.

Thermal generation and minority carrier diffusion

Outside the depletion region, minority carriers generated thermally in the quasi-neutral bulk can diffuse to the junction edge and be swept across. This diffusion current depends on the minority carrier diffusion length and the equilibrium minority carrier concentration, which itself depends on n_i². In practice, for silicon at room temperature, generation current in the depletion region dominates over diffusion current for low-leakage junctions, but the balance shifts with doping profile and temperature.

Temperature and electric field dependencies

Both leakage mechanisms are driven by n_i, and n_i follows an Arrhenius-like relationship with temperature, governed by the silicon bandgap energy E_g ≈ 1.12 eV. Diffusion current scales with n_i², generation current scales with n_i, but because n_i itself rises exponentially with temperature, both leakage components increase rapidly as the die heats up. This is the physical answer to why junction leakage increases exponentially with temperature: it is not an empirical curve-fit, it is a direct consequence of the thermal excitation of carriers across the silicon bandgap, compounded by the temperature dependence of carrier lifetime and trap occupancy. A rule of thumb worth keeping on a whiteboard: reverse leakage in a silicon junction roughly doubles for every 8-10°C rise near typical operating temperatures, though the exact coefficient depends on which mechanism dominates in a given process.

Electric field matters too. Higher reverse bias widens the depletion region (more generation volume) and increases local field strength, which can enhance trap-assisted tunneling — carriers hopping through a defect state partway across the barrier instead of over it. This field-enhanced emission, sometimes called Poole-Frenkel or trap-assisted tunneling depending on the mechanism, becomes significant in heavily doped, thin junctions typical of advanced CMOS source/drain extensions.

Exponential relationship to junction characteristics

The same silicon bandgap physics that makes reverse leakage temperature-sensitive is responsible for the extreme sensitivity of forward conduction to applied voltage, covered in Forward Bias: Exponential Current, Knee Voltage. The two phenomena share a common root: the diode equation's exponential term, which in forward bias amplifies current with voltage and in reverse bias collapses to the small, field- and temperature-dependent I_S this section has been describing.

Leakage Sources in Digital Circuits

Junction leakage vs. subthreshold and gate leakage

A modern CMOS transistor leaks through three largely independent paths. Subthreshold leakage flows from drain to source even when the gate-source voltage is below V_t, driven by the same thermal carrier statistics as a bipolar transistor's base current and controlled by the subthreshold slope. Gate leakage tunnels directly through the thin gate oxide (or high-k stack) between gate and channel. Junction leakage, the subject of this article, flows from drain or source diffusion through the body/well junction, driven by the reverse-bias physics above. They scale differently with voltage, temperature, and process corner, which is why a leakage budget needs to model them as separate terms rather than one lumped "off current."

Impact on standby and dynamic power consumption

Junction leakage is a DC phenomenon — it flows continuously whenever the junction is reverse-biased, which in a powered-up chip is essentially always, clock or no clock. That makes it a pure standby power cost, distinct from the switching energy captured in the dynamic power equation P = αCV²f. A block that never toggles still burns junction leakage power as long as its supply rails are live.

Leakage in CMOS logic gates and memory arrays

In a logic gate, every drain diffusion contributes its own reverse-biased junction to the leakage sum regardless of switching state. SRAM arrays are particularly exposed: millions of bit cells, each holding two cross-coupled inverters, sit idle for the vast majority of their operational life, and their aggregate junction and subthreshold leakage can rival the active power of the core logic around them. This is why cache-heavy designs invest heavily in retention and sleep strategies rather than accepting the raw array leakage.

Scaling effects at advanced nodes

As gate lengths shrank, doping concentrations in source/drain regions rose and junction depths fell to control short-channel effects. Higher doping narrows the depletion region but increases the electric field across it, pushing more of the leakage budget into field-enhanced generation and band-to-band tunneling. At 28 nm and below, junction leakage no longer behaves like the textbook diffusion-dominated diode; it is increasingly a tunneling-assisted phenomenon, which is one reason why datasheet leakage numbers at advanced nodes vary so much with fab corner and why margin for leakage variation has become its own line item in power sign-off.

Measurement and Modeling

Datasheet specifications and leakage parameters

Diode and transistor datasheets specify reverse leakage as I_R at a stated reverse voltage and temperature, typically 25°C, sometimes with a second point at an elevated temperature such as 85°C or 125°C to let designers estimate the thermal slope. For transistor-level leakage, foundry PDK documents report I_off per device width at nominal conditions and across process corners. Always check which temperature and voltage the number is specified at — a leakage spec at 25°C can understate the hot-case value by one to two orders of magnitude.

Temperature and voltage scaling of leakage current

Because leakage is exponential in both temperature and, more weakly, in reverse voltage, a single-point spec is only a starting point. Serious power budgeting requires either a vendor-supplied scaling model (often an empirical exponential fit to E_g and a voltage coefficient) or direct characterization across the expected operating envelope, since the junction leakage experienced at a hot, high-voltage corner can dominate total standby current even when it looks negligible at typical conditions.

SPICE model representation

BSIM and similar compact models represent junction leakage with dedicated parameters — saturation current density, grading coefficient, and often separate terms for area and perimeter components of the junction, since generation current scales with junction area while surface-related leakage scales with perimeter. A SPICE deck for a diode-connected junction typically exposes IS, N, and temperature coefficients directly:

.model DJUNC D(IS=1e-15 N=1.05 TT=1n EG=1.12 XTI=3)

Here XTI sets the temperature exponent for IS, directly encoding the bandgap-driven exponential behavior described above. Transistor-level netlists carry analogous junction parameters (JS, JSW, CJ, CJSW) attached to each MOSFET's drain/source diffusion areas and perimeters.

Practical measurement techniques

On the bench, junction leakage is measured by reverse-biasing the device under test through a precision source-measure unit capable of resolving currents in the picoamp to nanoamp range, inside a temperature-controlled chamber to separate thermal effects from voltage effects. On silicon, leakage is typically extracted using dedicated test structures — isolated diodes or transistor arrays with known area and perimeter — so that area and perimeter leakage components can be separated by regression across multiple device sizes.

Mitigation Techniques for Low-Power Design

Power gating and state retention

The most direct way to eliminate junction and subthreshold leakage in an idle block is to remove its supply entirely using a power-gating switch, typically a high-V_t header or footer transistor. Because junction leakage requires a reverse bias to exist, cutting the supply collapses the bias conditions that sustain it. The trade-off is that any state held in gated flops or SRAM is lost unless a retention cell or always-on retention rail is provided, which adds area and a wake-up latency penalty.

Substrate biasing approaches for leakage control

Rather than fully gating power, many designs modulate the body bias of transistors to control both subthreshold and junction leakage without losing state. Reverse body bias (RBB) increases the reverse bias across the body-well junction, widening the depletion region and raising V_t, which suppresses subthreshold leakage — though it can modestly increase junction leakage itself since the junction is biased harder. Forward body bias (FBB) does the opposite, trading leakage for speed. The mechanisms, circuit topologies, and silicon-level trade-offs of this technique are covered in Body Biasing: Forward Body Bias (FBB) and RBB for Leakage, which is the natural next read for engineers deciding whether body bias generation is worth the extra well isolation and charge pump overhead.

Threshold voltage optimization trade-offs

Most standard cell libraries at advanced nodes offer multiple V_t flavors — low, standard, and high — precisely because subthreshold and junction leakage both trade off against switching speed. Timing-critical paths get low-V_t cells despite their leakage cost; everything else is pushed to high-V_t cells during synthesis and place-and-route. This multi-V_t strategy does not touch junction leakage directly, since it is primarily a channel-doping and gate-oxide lever, but it indirectly manages total chip leakage by minimizing the population of inherently leaky devices.

Supply and substrate voltage management

Lowering V_dd reduces both dynamic power and some leakage components, but junction leakage is only weakly voltage-dependent compared to its temperature dependence, so supply scaling alone is a limited lever. The more effective knob is thermal: keeping junction temperature down through package selection, heat spreading, and DVFS policies that throttle before thermal runaway has an outsized effect on junction leakage specifically, given its exponential temperature coefficient.

Junction Leakage Impact on System Power Budget

Contribution to total chip leakage in modern processes

In older processes, junction leakage was a minor fraction of total static power, dwarfed by subthreshold leakage. At 28 nm and below, as doping profiles intensified and junctions were engineered abruptly to control short-channel effects, the junction component's share has grown — foundry PDK leakage breakdowns at advanced nodes often show it as a double-digit percentage of total off-state current, though the exact split should be taken from the process design kit's documented leakage model rather than assumed.

Standby power analysis and battery life implications

For battery-powered and always-on devices, standby current directly sets shelf life and sleep-mode battery drain. Because junction leakage persists as long as the supply rail is live, any block that cannot be fully power-gated — always-on domains, wake-up logic, RTC blocks — contributes its full leakage current continuously. Engineers should model this as a temperature-dependent current draw, not a fixed datasheet number, when projecting battery life across the product's expected thermal range.

Design methodology for leakage-aware circuits

A leakage-aware flow separates the leakage budget into subthreshold, gate, and junction components at the library characterization stage, applies corner-specific multipliers for voltage and temperature, and tracks each separately through synthesis, placement, and sign-off power analysis. Relying on a single lumped "static power" number from a typical-corner report routinely underestimates hot-corner standby power by a wide margin, because the exponential temperature dependence described earlier means the worst case and the typical case can differ by an order of magnitude or more.

Interaction with dynamic power in real workloads

In real operating profiles, dynamic and static power do not simply add independently — self-heating from switching activity raises junction temperature, which raises leakage, which raises temperature further in a positive feedback loop that thermal design must account for. A chip that looks comfortably within its power budget at a cool, idle corner can see its leakage-driven static power climb substantially once sustained workload-driven self-heating pushes junction temperatures toward the top of the operating range, which is why thermal and leakage models need to be co-simulated rather than treated as separate sign-off steps.