MOSFET as Switch: On-Resistance RDS(on) and Gate Charge Qg

Every buck converter, load switch, motor driver, and solid-state relay depends on the same trade-off: how fast can a MOSFET turn on and off, and how much power does it dissipate while doing so. Two datasheet parameters dominate that answer — on-resistance R_DS(on), which sets conduction loss, and total gate charge Q_g, which sets switching loss and drive requirements. Getting these wrong means a hot, inefficient, or unreliable power stage even if the rest of the circuit is correct.

The MOSFET as a Switch, Not an Amplifier

In switching applications the MOSFET is driven hard between two states:

• Off (cutoff): V_GS < V_th, drain current ≈ 0, the device blocks V_DS up to its breakdown rating.
• On (deep triode/ohmic region): V_GS is driven well above V_th (V_GS ≫ V_th, typically 10 V or 4.5 V logic-level parts), so the channel behaves like a voltage-controlled resistor: V_DS ≈ I_D · R_DS(on).

Unlike linear amplifier bias, there is no interest in the active/saturation region here except as a transient the device passes through as quickly as possible — that transition region is where switching loss is generated.

On-Resistance R_DS(on): Conduction Loss

In the ohmic region, R_DS(on) is the slope of the I_D–V_DS curve at the operating V_GS, dominated by:

• Channel resistance — decreases with (V_GS − V_th) and with gate area/technology.
• Drift region resistance — dominates in high-voltage MOSFETs; scales roughly with breakdown voltage as R_DS(on) ∝ BV^2.5 for a given technology, which is why 600 V MOSFETs have far higher R_DS(on) than 30 V parts of similar die size.
• Package/bond-wire resistance — matters more in low-voltage, high-current parts where die resistance is already very low (mΩ range).

Temperature dependence: R_DS(on) has a strong positive temperature coefficient, typically +0.4%/°C to +1%/°C, because channel mobility falls as temperature rises. This is a stabilizing property for current sharing in paralleled MOSFETs (a hotter device conducts less, so current redistributes) but means designs must use the datasheet's high-temperature R_DS(on), not the 25 °C value, for worst-case loss calculations.

Conduction loss:

P_cond = I_D(rms)² · R_DS(on)

Worked example

A synchronous buck low-side MOSFET carries an rms current of 3 A. Datasheet gives R_DS(on) = 15 mΩ at 25 °C, with a correction factor of 1.5× at 100 °C junction temperature.

R_DS(on)_hot = 15 mΩ × 1.5 = 22.5 mΩ
P_cond = (3 A)² × 22.5 mΩ = 9 A² × 0.0225 Ω = 202.5 mW

Check: at 3 A and 22.5 mΩ, V_DS = I·R = 3 × 0.0225 = 67.5 mV, and P = V·I = 0.0675 × 3 = 202.5 mW — consistent with the I²R form. This loss is independent of switching frequency; it is present at DC and scales only with current² and temperature-corrected resistance.

Gate Charge Q_g: The Real Driver Sizing Parameter

Gate threshold voltage and input capacitance (C_iss) are often used loosely to guess drive requirements, but capacitance is nonlinear with V_DS (dominated by the Miller capacitance C_gd, which varies strongly as the drain voltage swings). The datasheet's gate charge curve captures this correctly by plotting V_GS vs. charge delivered to the gate at constant drain current, and it has three characteristic regions:

V_GS
 |                _______________  ← V_GS(driver)
 |              /
 |    _________/   ← Miller plateau (V_DS falling)
 |   /
 |  /  ← Q_gs: charging Cgs, V_GS rising, V_DS still high, ID rising
 |_/________________________________ Qg
 0   Qgs      Qgs+Qgd(plateau)      Qg(total)

1. Q_gs (0 → V_th and beyond): charges the input capacitance; V_GS rises but V_DS and I_D haven't changed yet (device still off in this sub-segment, then I_D rises to full load current as V_GS crosses V_th up to the plateau).
2. Q_gd (Miller plateau): V_GS stays essentially flat while nearly all the gate current goes into discharging/charging C_gd as V_DS swings from its blocking value down to I_D · R_DS(on). This is the switching transition — the plateau width in charge (not time) is set by the drain voltage swing and C_gd, and is largely independent of gate drive voltage.
3. Q_g(total) or Q_g(on): charge to reach full gate drive voltage (e.g., 10 V or 4.5 V) with the device fully enhanced; includes some additional overdrive charge beyond the plateau.

Why Q_g matters more than capacitance alone

Because C_gd is voltage-dependent (large at low V_DS, small at high V_DS) and Miller feedback couples drain swing back into the gate, using a single C_iss number to predict turn-on/turn-off time is inaccurate. Q_g, measured under realistic bias, already integrates that nonlinearity — it's the number to use for two practical calculations:

Gate drive current for a target switching time:

I_g(avg) = Q_g / t_sw

Gate drive power (repetitive switching loss in the driver, not the MOSFET):

P_gate = Q_g · V_GS · f_sw

Worked example

A MOSFET has Q_g(total) = 25 nC at V_GS = 10 V. It switches at f_sw = 500 kHz, and the driver must complete the transition in 20 ns.

I_g(avg) = 25 nC / 20 ns = 1.25 A
P_gate = 25 nC × 10 V × 500 kHz = 250 nJ × 500,000 = 0.125 W

Check via energy: charging a gate to charge Q at voltage V dissipates roughly Q·V in the driver's resistive path per cycle (half in the driver pull-up, effectively modeled as Q·V total for the full charge/discharge cycle in many gate-drive-loss estimates); at 500 kHz, 125 mW of driver dissipation is a realistic, checkable order of magnitude for a mid-size power MOSFET — consistent with typical gate driver IC ratings.

Switching Loss and the Q_gd/Miller Plateau

The dominant hard-switching loss term is approximately:

P_sw ≈ ½ · V_DS · I_D · (t_rise + t_fall) · f_sw

where t_rise and t_fall are set largely by how fast the driver can push charge through the Miller plateau (Q_gd). A MOSFET with low R_DS(on) but large Q_gd (common in older or larger-die parts) can have higher total system loss at high switching frequency than a part with slightly higher R_DS(on) but much smaller Q_gd — this is the classic R_DS(on) vs. Q_g trade-off in MOSFET selection, often summarized by the figure of merit FOM = R_DS(on) × Q_g, where lower is better for high-frequency designs.

R_DS(on) vs. Q_g: Selection Trade-off

Practical Design Implications

• Always use R_DS(on) at operating temperature and operating V_GS, not the 25 °C headline number — datasheets give a normalized curve for both.
• Match driver current capability to Q_g and target switching time; an underpowered gate driver stretches time in the Miller plateau, directly increasing switching loss and can cause shoot-through in half-bridge designs.
• Add gate resistors deliberately, trading switching speed (and EMI) against loss — slower edges reduce ringing and voltage overshoot from parasitic inductance but increase P_sw.
• Check total gate drive power against the driver IC's dissipation rating at the intended switching frequency; Q_g × V_GS × f_sw can exceed small driver ICs' capability well before the MOSFET itself is thermally limited.
• Beware of Miller-induced false turn-on in half-bridge topologies: a fast V_DS edge on one device can inject current through the other device's C_gd into its gate, momentarily lifting V_GS toward V_th — mitigated with lower gate-loop impedance or negative gate drive.

Key Takeaways

• R_DS(on) sets conduction loss (P = I²·R_DS(on)) and must be derated for temperature using the datasheet's positive temperature coefficient.
• Q_g characterizes the total gate drive charge needed for a full switching transition and correctly captures the nonlinear, voltage-dependent Miller capacitance that a single C_iss value cannot.
• The Miller plateau (Q_gd) is where V_DS actually transitions and is the primary driver of switching loss and required drive current.
• Selecting a MOSFET is a trade-off between R_DS(on) (conduction loss) and Q_g (switching loss/drive burden), often compared via the figure of merit R_DS(on) × Q_g.
• Gate driver sizing must account for both peak current (Q_g/t_sw) and average power (Q_g·V_GS·f_sw), which can exceed the driver's rating independently of the MOSFET's own thermal limits.