MOSFET Structure: Gate Oxide, Channel, Threshold Voltage VT

Every MOSFET-based design decision — RDS(on) selection, gate drive voltage, level shifting, subthreshold leakage budgets — traces back to the physical structure of the device: a thin gate oxide sitting over a semiconductor channel whose conduction is switched on at a specific gate voltage, VT. Understanding why VT has the value it does, and what shifts it, is what separates picking a part number from actually designing around one.

Physical Structure

A MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is built as a four-terminal device: Gate, Source, Drain, and Body (Substrate). For an n-channel (NMOS) device on a p-type substrate:

        Gate (poly-Si or metal)
        ─────────────────────
        ░░░░ Gate Oxide (SiO₂) ░░░░   <- t_ox, a few nm
   n+ Source |  p-substrate  | n+ Drain
        ─────────────────────
             Body (B)

• Source and Drain: heavily doped n+ regions diffused into a p-type body, forming two back-to-back p-n junctions.
• Gate oxide: a thin insulating layer (SiO₂, or a high-k dielectric in modern nodes) separating the conductive gate from the body. It has capacitance per unit area Cox = εox / tox, where εox ≈ 3.45×10⁻¹¹ F/m for SiO₂ and tox is the oxide thickness (1–2 nm in advanced logic, tens of nm in discrete power MOSFETs).
• Gate: originally metal, then polysilicon (hence "MOS" persisting even with poly gates), now often back to metal gates in advanced CMOS.
• Body: the substrate, which together with source/drain forms the junctions that must stay reverse-biased for normal operation.

With no gate voltage applied, the two n+ regions are isolated by the p-type body — no continuous n-type path exists, so the device is OFF regardless of drain voltage (ignoring leakage).

Channel Formation: Inversion

Applying a positive gate-to-source voltage VGS (for NMOS) attracts electrons toward the body surface beneath the oxide. As VGS increases through several regimes:

1. Accumulation (VGS very negative, NMOS): majority carriers (holes) pulled to the surface — no channel.
2. Depletion (VGS moderately positive but below VT): holes are repelled from the surface, forming a depletion region — still no conductive n-type path.
3. Inversion (VGS ≥ VT): enough electrons accumulate at the surface to form a thin n-type layer connecting source to drain — the channel. This is called strong inversion.

The channel is not a physical doped region; it's an induced sheet of minority carriers held at the oxide-silicon interface by the vertical electric field from the gate. Its conductivity is controlled continuously by VGS − VT (the "overdrive" voltage) — this is the entire basis of MOSFET action as a voltage-controlled resistor/current source.

Threshold Voltage VT: What Sets It

VT is the gate voltage at which strong inversion begins (by convention, when the inversion charge density equals the bulk doping charge density). The standard first-order expression:

VT = VFB + 2·φF + √(2·εsi·q·NA·(2·φF)) / Cox

Where:

• VFB — flat-band voltage (depends on gate/semiconductor work function difference and oxide charge)
• φF = (kT/q)·ln(NA/ni) — Fermi potential of the substrate
• NA — body (substrate) doping concentration
• εsi — permittivity of silicon
• Cox = εox/tox — oxide capacitance per unit area

The practical takeaway from this formula, without grinding through the derivation every time:

Body effect deserves its own note because it bites in real circuits (source followers, cascodes, series switches without isolated bodies):

VT = VT0 + γ·(√(VSB + 2φF) − √(2φF))

γ is the body-effect coefficient (typically 0.3–0.5 V^0.5 for older bulk processes). Whenever the source isn't tied to the body (common in NMOS pull-up stacks or cascode switches), VT effectively rises as VSB increases, reducing available overdrive.

Worked Example: Estimating VT Shift from Oxide Scaling

Suppose a device has tox = 100 nm and a measured VT0 = 1.2 V at VSB = 0. A process shrink reduces tox to 20 nm, keeping all doping and work-function terms unchanged. Estimate the new threshold.

Only the term √(2·εsi·q·NA·(2φF)) / Cox scales with tox (Cox = εox/tox, so this term scales linearly with tox). Assume this depletion-charge term accounts for 0.5 V of the original 1.2 V VT0 (a typical split, with the rest from VFB + 2φF ≈ 0.7 V).

Term_old = 0.5 V  at tox = 100 nm
Term_new = Term_old × (tox_new / tox_old) = 0.5 × (20/100) = 0.1 V
VT_new = 0.7 V + 0.1 V = 0.8 V

Check: the fixed part (VFB + 2φF ≈ 0.7 V) is untouched by oxide scaling — only the charge term shrinks because Cox rose 5×. The result, VT dropping from 1.2 V to 0.8 V, matches the well-known trend that thinner gate oxides in scaled processes come with lower native VT — which is exactly why modern logic-level MOSFETs turn on around 0.3–0.7 V while older discrete power MOSFETs need 2–4 V.

Design Implications

• Gate drive voltage selection: a power MOSFET with VT = 4 V needs a gate driver capable of pulling well above that (typically 10–15 V) to reach low RDS(on); driving it from a 3.3 V logic output leaves it in or near cutoff.
• Logic-level vs. standard MOSFETs: "logic-level" parts are specifically processed (thinner oxide, tailored doping) to guarantee full enhancement from 5 V or 3.3 V gate drive — check the datasheet's VT test condition, not just the typical value.
• Body effect in switch stacks: in a cascoded or series NMOS switch where the lower device's source isn't grounded, its effective VT rises, reducing headroom — must be accounted for in analog switch and level-shifter design.
• Temperature dependence: VT decreases with temperature (roughly −2 to −4 mV/°C for silicon), the opposite direction of RDS(on) drift dominated by mobility — this partial cancellation is why some power MOSFETs show relatively flat VGS(th) vs. temperature drive requirements even as conduction losses rise.
• Subthreshold leakage: VGS below VT doesn't mean zero current — subthreshold conduction (exponential in VGS) sets the leakage floor and matters for ultra-low-power and always-on rail designs.

Key Takeaways

• The MOSFET's gate oxide and induced channel — not a physically doped path — are what connect source to drain; conduction depends entirely on the vertical field-induced inversion layer.
• Threshold voltage VT is the gate voltage marking the onset of strong inversion, set by flat-band voltage, substrate doping, and oxide capacitance (Cox = εox/tox).
• Thinner gate oxide (higher Cox) lowers VT — the physical reason logic-level and scaled-node MOSFETs have much lower thresholds than older discrete power devices.
• The body effect raises effective VT whenever VSB > 0, which matters in cascodes, switch stacks, and any topology where the source floats above the body potential.
• VT drifts negative with temperature, RDS(on) drifts positive — both must be checked across the operating temperature range, not just at 25 °C.