Analog Electronics
Continuous-signal circuit design: amplifiers, filters, oscillators, signal conditioning, and precision measurement circuits.
360 topics · 79 with articles
Intern Engineer· 40
- AC Power: Real (P), Reactive (Q), Apparent (S), Power Factor
- Bode Plot: Magnitude and Phase vs. Frequency
- Capacitor: Charge, Energy, V-I Relationship (I = C dV/dt)
- Circuit Sensitivity Analysis: ∂H/∂Component
- Decibel (dB): Voltage, Current, and Power Ratios
- Elmore Delay Model for RC Interconnects
- Energy Storage and Duality in Circuits
- Fourier Series: Harmonic Decomposition of Signals
- Impedance (Z), Admittance (Y), Reactance (X)
- Inductor: Flux, Energy, V-I Relationship (V = L dI/dt)
- Kirchhoff's Current Law (KCL) and Node Analysis
- Kirchhoff's Voltage Law (KVL) and Mesh Analysis
- LTspice: Schematic Entry and Simulation Basics
- Laplace Transform for Circuit Analysis
- Lumped vs. Distributed Element Circuits
- Maximum Power Transfer Theorem (RL = RS)
- Millman's Theorem for Parallel Voltage Sources
- Non-Ideal Components: Parasitic R, L, C Effects
- Norton's Theorem: Equivalent Current Source
- Ohm's Law: V = IR and Power Dissipation P = IV
- Phasor Representation and Complex Impedance
- RC Circuit: Time Constant τ = RC, Charging/Discharging
- RL Circuit: Time Constant τ = L/R, Transient Response
- RLC Parallel Circuit: Anti-Resonance and Impedance Peak
- RLC Series Circuit: Resonance, Q-Factor, Bandwidth
- Reciprocity Theorem and Its Applications
- SPICE Simulation: DC, AC, Transient Analysis
- Series and Parallel Resistor Combinations
- Signal Flow Graph and Mason's Gain Formula
- Signal Ground, Chassis Ground, and Earth Ground
- Signal Integrity: Reflection, Crosstalk, Termination
- Skin Effect and High-Frequency Conductor Loss
- Source Transformation: Thevenin ↔ Norton
- Superposition Theorem for Linear Circuits
- Thevenin's Theorem: Equivalent Voltage and Resistance
- Transfer Function H(s) and Poles/Zeros
- Transmission Line Theory: Characteristic Impedance Z0
- Two-Port Network Parameters: Z, Y, H, ABCD
- Voltage Divider and Current Divider Rules
- Wye (Y) and Delta (Δ) Network Transformation
Junior Engineer· 40
- BJT Current Gain (β, hFE) and Base Current Control
- BJT Frequency Response: fT and fmax
- BJT Operating Regions: Active, Saturation, Cutoff, Breakdown
- BJT Small-Signal Model: Hybrid-π and T-Model
- Bipolar Junction Transistor (BJT): NPN and PNP Structure
- Complementary MOS (CMOS): NMOS + PMOS Pairing
- Crystal Structure: Silicon Lattice and Covalent Bonds
- Depletion Region: Width, Electric Field, Space Charge
- Device Matching and Thermal Runaway in BJT Pairs
- Diode I-V Characteristic: Shockley Equation
- Early Effect: VA, Output Resistance (ro) in BJT
- Energy Band Theory: Valence Band, Conduction Band, Bandgap
- Extrinsic Semiconductor: n-type (Donor) and p-type (Acceptor)
- Forward Bias: Exponential Current, Knee Voltage
- GaN HEMT: Two-Dimensional Electron Gas (2DEG)
- IGBT: Structure, Characteristics, and Applications
- Intrinsic Semiconductor: Carrier Concentration (ni)
- JFET: N-Channel and P-Channel, Pinch-Off Voltage
- LED: Electroluminescence and Wavelength Selection
- MOSFET Short-Channel Effects: DIBL, Velocity Saturation
- MOSFET Small-Signal Model: gm, gds, Cgs, Cgd
- MOSFET Structure: Gate Oxide, Channel, Threshold Voltage VT
- MOSFET as Switch: On-Resistance RDS(on) and Gate Charge Qg
- Moore's Law and Semiconductor Scaling Trends
- NMOS/PMOS I-V Characteristics: Triode and Saturation Regions
- Optoelectronics: Optocoupler Isolation and CTR
- PIN Diode: Microwave Switch and Attenuator Applications
- Photodiode: Photovoltaic and Photoconductive Modes
- Power MOSFET: SOA (Safe Operating Area) and Breakdown
- Reverse Bias: Leakage Current, Breakdown Mechanisms
- Schottky Diode: Metal-Semiconductor Junction, Low VF
- SiC MOSFET: Wide Bandgap Advantages for Power
- Thyristor (SCR): Triggering, Latching, Commutation
- Transistor Data Sheet Interpretation: Key Parameters
- Triac and Diac: AC Power Control
- Tunnel Diode: Negative Resistance Region
- Varactor Diode: Junction Capacitance vs. Voltage (CV Curve)
- Zener Diode Voltage Regulator Circuit Design
- Zener Diode: Zener Breakdown and Avalanche Breakdown
- p-n Junction Formation and Built-In Potential (V_bi)
Middle Engineer· 120
- Absolute Value Circuit (Full-Wave Rectifier)
- Active Band-Pass Filter: Center Frequency and Q Calculation
- Active Clamp and Limiter Circuits
- All-Pass Filter: Constant Amplitude, Phase Shift
- Amplifier Noise Sources: Thermal, Shot, Flicker (1/f)
- Anti-Aliasing Filter: Design Before ADC Sampling
- Antilog (Exponential) Amplifier: Vout = Vref * e^(Vin/K)
- Auto-Zero and Chopper-Stabilized Op-Amps
- BJT Biasing: Fixed Bias, Emitter Bias, Voltage Divider Bias
- BJT Cascode Amplifier: High Gain × Bandwidth Product
- Bessel Filter: Maximally Flat Group Delay (Linear Phase)
- Biquad Filter: Fleischer-Tow, Tow-Thomas Topology
- Butterworth Filter: Maximally Flat Passband Response
- CE Amplifier with Emitter Resistance RE (Bypassed/Unbypassed)
- CMOS Inverter as Amplifier: Voltage Gain and Biasing
- CS Amplifier with Source Degeneration RS
- Cascading Biquad Sections: Gain Distribution Strategy
- Chebyshev Type I: Equiripple Passband, Sharp Roll-Off
- Chebyshev Type II: Equiripple Stopband Response
- Chopper-Stabilized Amplifier for Low-Frequency Drift
- Common-Base (CB) Amplifier: High-Frequency, Low Rin
- Common-Collector (CC) / Emitter Follower: Buffer Stage
- Common-Drain (CD) / Source Follower: Low Rout Buffer
- Common-Emitter (CE) Amplifier: Gain, Rin, Rout
- Common-Gate (CG) Amplifier: High-Frequency, Low Rin
- Common-Mode Rejection Ratio (CMRR) Measurement
- Comparator vs. Op-Amp: Slew Rate and Open-Loop Use
- Compensation Techniques: Lead, Lag, Lead-Lag
- Component Selection for Precision Filters (1% Resistors, NP0 Caps)
- Current Mirror: Simple, Wilson, Cascode, Wide-Swing
- Current-Feedback Amplifier (CFA): Bandwidth Independence
- Darlington Pair: High Current Gain Configuration
- Decompensated Op-Amp: Use with High Gain Only
- Difference Amplifier: CMRR and Resistor Matching
- Differential Amplifier (BJT): CMRR and Tail Current Source
- Differential Pair (MOSFET): Tail Current Source Design
- Differentiator Circuit: Output = -RC dVin/dt
- Digital vs. Analog Filter Trade-offs
- Distortion: THD (Total Harmonic Distortion) Measurement
- Dynamic Range and Spurious-Free Dynamic Range (SFDR)
- EMI Filtering: Common-Mode and Differential-Mode
- Elliptic (Cauer) Filter: Equiripple in Both Bands
- Filter Approximation Selection: Trade-offs Summary
- Filter Classification: LP, HP, BP, Band-Stop (Notch)
- Filter Measurement: Frequency Response with Network Analyzer
- Filter Order and Roll-Off Rate: -20 dB/decade per Order
- Filter PCB Layout: Guard Rings, Ground Plane, Shielding
- Filter Prototype Tables: Normalized Component Values
- Filter Q Factor: Effect on Stability and Sensitivity
- Frequency Response: Low-Frequency Poles (Coupling Caps)
- Friis Formula for Cascaded Noise Figure
- Fully Differential Amplifier: Output Common-Mode Feedback
- Gain-Bandwidth Product (GBW) and its Trade-offs
- Gain-Bandwidth Product (GBW): 1 MHz, 10 MHz Devices
- Gm-C (Transconductor-Capacitor) Filter for IC Integration
- Group Delay and Phase Linearity in Filter Design
- High-Frequency Response: Miller Effect and Pole Splitting
- High-Order Filter Stability and Dynamic Range
- I-to-V Converter: Transimpedance Amplifier (TIA)
- Ideal Op-Amp Assumptions: Infinite Gain, Rin, CMRR
- Impedance Scaling and Frequency Scaling of Prototypes
- Input Bias Current (IB) and Offset Current (IOS)
- Input Offset Voltage (VOS): Nulling and Drift
- Input-Referred Noise Voltage and Current
- Instrumentation Amplifier (INA): 3 Op-Amp Configuration
- Instrumentation Amplifier: High CMRR, Adjustable Gain
- Integrator Circuit: Output = -(1/RC)∫Vin dt
- Intermodulation Distortion (IMD): IP2, IP3 Definition
- Inverting Amplifier: Gain = -RF/Rin, Virtual Ground
- Inverting Schmitt Trigger: Hysteresis and Threshold Voltages
- KHN (Kerwin-Huelsman-Newcomb) State-Variable Filter
- Logarithmic Amplifier: Vout = K ln(Vin/Vref)
- Long-Tailed Pair: Differential Mode vs. Common Mode
- Low-Pass to Band-Pass Frequency Transformation
- Low-Pass to High-Pass Frequency Transformation
- MFB Low-Pass Filter: Inverting, High Q Capability
- MOSFET Cascode Amplifier: Improved Output Resistance
- MOSFET Common-Source (CS) Amplifier: Gain and Impedance
- Miller Approximation: Effective Input Capacitance
- Multiple Feedback (MFB) Band-Pass Filter Design
- Multiplier / Divider Using Log-Antilog Technique
- Multistage Amplifier: RC-Coupled, Direct-Coupled
- Noise Figure (NF) and Noise Temperature Calculation
- Noise Performance of Active Filters
- Noise in Op-Amp Circuits: En, In, Noise Gain
- Non-Inverting Amplifier: Gain = 1 + RF/Rin
- Non-Inverting Schmitt Trigger: Trip Points Calculation
- Notch (Twin-T) Filter: 60 Hz Hum Rejection
- Op-Amp Slew Rate: Definition, Measurement, Impact
- Op-Amp Stability: Phase Margin and Gain Margin
- Open-Circuit and Short-Circuit Time Constants Method
- Output Swing, Short-Circuit Current, Latch-Up
- Peak Detector Circuit: Charge and Hold
- Pole-Zero Placement and Filter Shape
- Power Gain, Voltage Gain, and Available Gain Definitions
- Power Supply Rejection Ratio (PSRR) Analysis
- Precision Full-Wave Rectifier Configuration
- Precision Half-Wave Rectifier (Superdiode)
- Precision Op-Amp Selection: OPA277, AD8221, LT1028
- Q-Point Design: DC Load Line and Bias Stability
- RF Low-Noise Amplifier (LNA) Design Principles
- Reconstruction (Smoothing) Filter: After DAC Output
- SPICE Op-Amp Macro-Model: Level 1, 2, 3
- Sallen-Key High-Pass Filter: Component Transformation
- Sallen-Key Low-Pass Filter: 2nd-Order Topology
- Sample-and-Hold Circuit: Acquisition and Hold Mode
- Self-Bias and Active Load MOSFET Amplifier
- Sensitivity Analysis: Component Tolerance Effect on Response
- Single-Supply Op-Amp Design: Rail-to-Rail Operation
- State-Variable Filter: LP, BP, HP, Notch Simultaneously
- Summing Amplifier (Inverting and Non-Inverting)
- Switched-Capacitor Filter: Principle and Clock Frequency
- Thermal Stability Factor S and Temperature Effects
- Transconductance Amplifier (OTA) Basics
- Tunable Active Filter: Voltage-Controlled Frequency
- Unity-Gain Frequency (fT) Measurement and Interpretation
- V-to-I Converter (Howland Current Pump)
- Variable Gain Amplifier (VGA): Gilbert Cell
- Voltage Follower (Unity Gain Buffer): High Rin, Low Rout
- Wien Notch Filter: Adjustable Notch Frequency
Senior Engineer· 80
- 555 Timer: Astable Mode — Frequency and Duty Cycle
- 555 Timer: Monostable Mode — Pulse Width Calculation
- Audio Amplifier PCB Layout: Star Ground, Decoupling Strategy
- Audio Power Amplifier: THD+N, SNR, Output Power Specs
- Balanced (Push-Pull) RF Amplifier with 180° Hybrids
- Barkhausen Stability Criterion: Loop Gain = 1, Phase = 0°
- Bootstrap Technique for Rail-to-Rail Output Swing
- Charge Pump: UP/DOWN Current Sources, Leakage
- Clapp Oscillator: Series-Tuned Colpitts Variant
- Class A Amplifier: Conduction Angle 360°, Low Efficiency (~25%)
- Class AB Amplifier: Quiescent Bias to Reduce Crossover Distortion
- Class B Amplifier: Conduction Angle 180°, Crossover Distortion
- Class C Amplifier: Narrow Conduction, High Efficiency for RF
- Class D Amplifier: Switching (PWM), >90% Efficiency
- Class D Gate Drive, Dead-Time, and EMI Filter Design
- Class E Amplifier: ZVS (Zero-Voltage Switching) Operation
- Class F Amplifier: Harmonic Tuning for High Efficiency
- Colpitts Oscillator: LC Tank with Capacitive Feedback
- Crossover Distortion: Cause, THD Impact, and Bias Solution
- Crystal Equivalent Circuit: Cs, Cp, L, R Series Model
- Crystal Oscillator: Piezoelectric Effect, Series/Parallel Mode
- DLL (Delay-Locked Loop): Phase Alignment Application
- Darlington Power Stage: High Current Gain for Output
- Digital Pre-Distortion (DPD) for RF PA Linearization
- Doherty Amplifier: Efficiency at Back-Off Power
- Emitter Follower Output Stage: Low Rout for Current Drive
- Envelope Tracking Power Supply for RF PA
- FLL (Frequency-Locked Loop): Frequency Stabilization
- Feedback in Power Amplifiers: Stability and Distortion
- Fractional-N PLL: Sigma-Delta Modulator for Fraction
- GaN RF Power Amplifier: High Power Density Advantage
- Harmonic Filter Design for RF PA Output
- Hartley Oscillator: LC Tank with Inductive Feedback
- Heat Sink Calculation: Rθ(jc), Rθ(cs), Rθ(sa) Chain
- Impedance Matching Networks: L, Pi, T for RF PA
- Integer-N PLL Frequency Synthesizer: N Divider
- Junction Temperature: TJ = TA + PD × Rθ(ja)
- LC VCO: Varactor-Tuned, Phase Noise Optimization
- Leeson's Model for Oscillator Phase Noise
- Loudspeaker Crossover Network: Passive vs. Active
- Oscillator Start-Up: Negative Resistance and Initial Conditions
- PA Bias Circuits: Active Bias, Temperature Compensation
- PA Protection: Over-Temperature, Over-Current, VSWR Fold-Back
- PLL Frequency Multiplication and Division
- PLL Lock Time, Settling Time, and Loop Bandwidth
- PLL Loop Filter: Passive (R-C) and Active (Op-Amp) Design
- PLL Noise Transfer Functions: In-Band and Out-of-Band
- PLL Phase Detector: XOR, Phase-Frequency Detector (PFD)
- PLL Simulation with Matlab/Simulink and SPICE
- PLL Stability: Phase Margin from Open-Loop Bode Plot
- PLL VCO Integration and KVCO Matching
- PLL as FM Demodulator and Clock Recovery
- Phase Noise: L(f) Definition, 1/f^3, 1/f^2 Regions
- Phase-Locked Loop (PLL): Basic Architecture and Blocks
- Power Amplifier Classes Overview: A, B, AB, C, D, E, F
- Power Amplifier Test: Pout, Gain, P1dB, IP3, PAE Measurement
- Power Op-Amp (OPA549, LM3886): High-Voltage, High-Current
- Power Supply Noise Sensitivity of VCO (PSRR)
- Power Transistor Selection: fT, VCEO, IC(max), hFE
- Push-Pull Output Stage: Complementary Symmetry (NPN+PNP)
- Quadrature Oscillator: I and Q Signal Generation
- Quasi-Complementary Output Stage: NPN + NPN Configuration
- RC Phase-Shift Oscillator: f = 1/(2π RC√6)
- RF PA Linearity: AM-AM, AM-PM Compression Curves
- RF Power Amplifier (PA): Load Pull, PAE (Power Added Efficiency)
- Reference Spurs in PLL: Causes and Mitigation
- Relaxation Oscillator: Schmitt Trigger + RC Timing
- Ring Oscillator: Number of Stages, Frequency vs. Delay
- Ring VCO for CMOS: Wideband, High Phase Noise
- Safe Operating Area (SOA): Voltage, Current, Power Limits
- Spread-Spectrum Clock (SSC): EMI Reduction
- Stability of RF PA: K-Factor and Stability Circles
- Sub-Harmonic Oscillation and Lock-Range Analysis
- Switching Power Amplifier vs. Linear: EMI and Efficiency
- TCXO and OCXO: Temperature Compensation Techniques
- Thermal Runaway in Power Transistors: VBE Temperature Drift
- Thermal Stability Design: Emitter Resistors and VBE Multiplier
- VCXO (Voltage-Controlled Crystal Oscillator) Design
- Voltage-Controlled Oscillator (VCO): KVCO and Tuning Range
- Wien Bridge Oscillator: f = 1/(2πRC), AGC Technique
Staff Engineer· 40
- Analog IC Floorplan: Isolation, Shielding, Supply Routing
- Analog MUX and Transmission Gate Design
- Analog Switch: Ron, Coff, Charge Injection, Clock Feedthrough
- Auto-Zero Technique for Offset Cancellation
- BGR Temperature Coefficient Trimming
- Bandgap Reference (BGR): Brokaw and Widlar Topologies
- CMOS Differential Pair: Transconductance gm and Tail Current
- Cascode Compensation and Right-Half-Plane Zero Cancellation
- Charge Pump Circuit for Voltage Doubling / Inversion
- Chopper Stabilization for 1/f Noise and Offset Reduction
- Comparator: Hysteresis, Propagation Delay, Metastability
- Current Mirror: Simple (1:1), Ratioed, Cascode, Wilson
- Current Steering DAC: Glitch Energy and Deglitcher
- DAC Architectures: R-2R Ladder, Current Steering, Segmented
- DAC Nonlinearity: DNL, INL, Monotonicity
- Dynamic Comparator: Latch-Based, Low Power
- Flash ADC: Resistor Ladder, Comparator Bank, Thermometer Code
- Frequency Compensation: Miller, Feedforward, Nested Miller
- Fully Differential Op-Amp and Common-Mode Feedback (CMFB)
- Gain-Bandwidth Product vs. Power Trade-off in Op-Amp
- LDO Regulator: Pass Device, Error Amplifier, Feedback
- LDO Stability: ESR Zero and Output Capacitor Selection
- Layout Techniques: Common-Centroid, Interdigitation, Guard Ring
- One-Stage Folded-Cascode Op-Amp: High Gain, Wide Swing
- Op-Amp Input Offset Voltage: Sources and Cancellation
- Oscillator Phase Noise Optimization in IC
- PTAT (Proportional to Absolute Temperature) Current Source
- Phase-Locked Loop (PLL) IC Block Design
- Pipeline ADC: Residue Amplifier, Stage Gain Error
- Rail-to-Rail Input Stage: N+P Parallel Differential Pairs
- Rail-to-Rail Output Stage: Common-Source with Feedback
- Recycling Folded-Cascode (RFC): Improved gm Efficiency
- Regulated Cascode (Gain-Boost): Ultra-High Output Resistance
- SAR ADC: Capacitor DAC, Successive Approximation Logic
- Sample-and-Hold Circuit: Track and Hold, Pedestal Error
- Sigma-Delta ADC: Oversampling, Noise Shaping, OSR
- Telescopic Cascode Op-Amp: Maximum Speed Architecture
- Two-Stage Op-Amp: Differential Input + Common-Source Output
- VCO Design for PLL: LC and Ring Implementations
- Wide-Swing Cascode Current Mirror for High Rout
Distinguished Engineer· 40
- ADC Dynamic Performance: SNDR, SFDR, ENOB, THD
- AI-Assisted Analog Circuit Sizing and Optimization
- Analog Neural Network Circuits: Sigmoid, Synapse Cell
- Analog Signal Conditioning for Industrial (4-20 mA) Loop
- Background and Foreground ADC Calibration Techniques
- Bioelectronics Front-End: ECG, EEG, EMG Signal Chains
- CT-SDM Excess Loop Delay and Compensation
- CT-SDM Loop Filter Design: RC Integrators, GmC
- Chiplet Integration: Analog Die in Multi-Die Package
- Continuous-Time Sigma-Delta ADC (CT-SDM) Architecture
- DAC Calibration: Output Impedance, Glitch Reduction
- Data Converter Testing: Histogram, FFT, Sine-Fit Methods
- Discrete-Time Sigma-Delta ADC (DT-SDM): SC Implementation
- Hall Effect Sensor Interface and Linearization
- High-Resolution Sensor Interface: Weigh Scale, Pressure, Temp
- High-Speed ADC PCB Layout: Differential Input, Decoupling
- High-Speed Current-Steering DAC: Segmented Architecture
- In-Memory Analog Compute: Memristor Crossbar Array
- Incremental ADC for Low-Speed, High-Precision Sensing
- Isolated Amplifier Design: Magnetic and Capacitive Isolation
- MASH (Multi-Stage Noise Shaping) SDM Architecture
- MEMS Sensor Interface: Capacitive Readout Circuit
- Mismatch Error Shaping and Calibration Algorithms
- Mixed-Signal SoC Integration: Substrate Coupling, Guard Rings
- Multi-Bit Sigma-Delta: Internal DAC Mismatch and DEM
- Neuromorphic Analog Circuit Concepts
- Noise-Shaping Orders: 1st, 2nd, Higher-Order SDM
- Optical Sensor: Photodiode TIA, APD Bias, SNR Optimization
- Phase Noise Measurement: Cross-Correlation and Reference Oscillator
- Pipelined SAR ADC: Hybrid Architecture
- Post-Silicon Calibration: Laser Trimming, OTP Fuse, EEPROM
- SAR ADC with Redundancy and Noise-Averaging Techniques
- SC Amplifier: Precision Gain without Resistors
- SC Filter Design: Bilinear and Euler Transformation
- SC Integrator: Delaying and Non-Delaying Types
- Sample-and-Hold Amplifier (SHA): Bandwidth and THD
- Sigma-Delta DAC: Digital Interpolation and Noise Shaping
- Spurious Signal Analysis and Isolation Techniques
- Switched-Capacitor Circuits: Charge Conservation Principle
- Time-Interleaved ADC: Gain, Offset, and Timing Mismatch