Varactor Diode: Junction Capacitance vs. Voltage (CV Curve)

A varactor (varicap) diode is just a reverse-biased p-n junction operated deliberately for its voltage-dependent depletion capacitance rather than its rectifying action. Every diode and every MOSFET gate exhibits this same junction-capacitance-vs-voltage behavior as a parasitic; the varactor turns that "parasitic" into the tuning element of VCOs, RF tank circuits, phase shifters, and varactor-tuned filters. Understanding the CV curve quantitatively — not just qualitatively "more reverse bias, less capacitance" — is what lets you size a tuning range, predict AM-to-FM noise conversion in an oscillator, and choose between an abrupt and a hyperabrupt junction.

Physical Origin: Depletion Capacitance

A reverse-biased p-n junction has a depletion region depleted of free carriers, bounded by charge on either side (ionized donors on the n-side, ionized acceptors on the p-side). This structure is electrically a parallel-plate capacitor whose "plate separation" is the depletion width W, which itself grows with reverse voltage:

W(V) = √( 2ε(V_bi + V_R) / (q·Neff) )

where V_bi is the built-in potential, V_R is the applied reverse bias, Neff is the effective doping (series combination of Nd and Na for an asymmetric junction), and ε is the semiconductor permittivity.

The total junction capacitance follows directly:

Cj(V) = ε·A / W(V)

Since W increases with V_R, Cj decreases with reverse bias — this is the entire mechanism. No minority-carrier storage or diffusion capacitance is involved (that's a forward-bias phenomenon); the varactor operates exclusively in reverse bias to keep leakage low and Q high.

The General CV Law

Combining the two expressions above gives the standard varactor equation:

Cj(V) = Cj0 / (1 + V_R/V_bi)^m

• Cj0 — zero-bias junction capacitance (at V_R = 0)
• V_bi — built-in potential (~0.6–0.7 V for silicon)
• m — grading coefficient, set by the doping profile

The exponent m is the single most important spec for choosing a varactor: it sets how sharply capacitance falls with voltage, which in turn sets tuning sensitivity Kvco in an oscillator.

Worked Example

A silicon abrupt-junction varactor has Cj0 = 20 pF at V_R = 0, V_bi = 0.65 V, and m = 0.5. Find Cj at V_R = 1 V and V_R = 9 V, and the resulting tuning ratio.

At V_R = 1 V:

Cj = 20 pF / (1 + 1/0.65)^0.5
   = 20 pF / (1 + 1.538)^0.5
   = 20 pF / (2.538)^0.5
   = 20 pF / 1.593
   ≈ 12.6 pF

At V_R = 9 V:

Cj = 20 pF / (1 + 9/0.65)^0.5
   = 20 pF / (1 + 13.85)^0.5
   = 20 pF / (14.85)^0.5
   = 20 pF / 3.854
   ≈ 5.19 pF

Tuning ratio (max/min capacitance over this range):

Cj(1V) / Cj(9V) = 12.6 / 5.19 ≈ 2.43:1

Check: capacitance should fall monotonically with reverse bias and the curve should flatten at high V_R (square-root-in-denominator behavior means diminishing returns). 12.6 pF → 5.19 pF is a drop of about 59% (more than half) despite less than a 9× increase in the (V_R + V_bi) term — consistent with the m = 0.5 power law's compressive, but still substantial, rolloff. Units check: Cj0 in pF, the bracketed term is dimensionless, so the result is in pF. ✓

Impact on Oscillator Tuning

In an LC tank, resonant frequency is f₀ = 1/(2π√(LC)). If the varactor is the dominant tuning capacitance, substituting the CV law gives:

f₀(V) = 1 / (2π√(L·Cj0)) · (1 + V_R/V_bi)^(m/2)

• With m = 0.5 (abrupt), frequency varies as (1+V_R/V_bi)^0.25 — a fairly compressed, nonlinear tuning curve, steep at low bias and flat at high bias.
• Hyperabrupt junctions (m closer to 1–2) push frequency-vs-voltage closer to linear, which is why VCOs used inside PLLs almost always specify hyperabrupt varactors: a linear Kvco (Hz/V) simplifies loop filter design and keeps loop bandwidth/phase margin consistent across the tuning range.
• Because dCj/dV is largest at low V_R, oscillator phase noise sensitivity to supply/control-line noise (AM-to-FM and voltage noise conversion) is worst at the low end of the tuning range — a practical reason to bias varactor-tuned VCOs away from V_R ≈ 0 where possible.

Design and Practical Considerations

• Q factor vs. bias: varactor Q = 1/(ω·Rs·Cj), where Rs is the series resistance of the undepleted semiconductor. As V_R increases, Cj drops but W (and hence undepleted, resistive material) shrinks too, so Q typically improves with more reverse bias — another reason not to run varactors near zero bias.
• Maximum reverse voltage: must stay below the junction breakdown voltage with margin; exceeding it causes avalanche current and loss of tuning control, not just device damage.
• Series resistance and self-resonance: at high RF, package parasitics (bond wire inductance, lead capacitance) limit the usable frequency range — always check the datasheet's S-parameter or Q-vs-frequency curves, not just the DC CV curve.
• Temperature drift: V_bi decreases with temperature (~-2 mV/°C for silicon), shifting the CV curve and hence f₀ — a factor in VCO temperature compensation.
• Linearization technique: two varactors in series, back-to-back (anode-to-anode or cathode-to-cathode), cancel second-harmonic distortion from large RF swing across the junction and are standard practice in tunable filters and antenna matching networks.

Key Takeaways

• Varactor capacitance comes purely from depletion-region width modulation under reverse bias: Cj(V) = Cj0 / (1 + V_R/V_bi)^m.
• The grading coefficient m (0.5 abrupt, 0.33 linear-graded, up to ~2 hyperabrupt) determines tuning sensitivity and linearity — hyperabrupt junctions give the most linear frequency-vs-voltage response, preferred in PLL VCOs.
• Capacitance change is steepest at low reverse bias and flattens at high bias — a fundamental nonlinearity that affects both tuning range and noise sensitivity.
• Q generally improves with increasing reverse bias as series resistance drops with shrinking undepleted region — avoid biasing near V_R = 0 for high-Q applications.
• Back-to-back varactor pairs cancel even-order distortion and are the standard configuration in RF tuning and matching circuits.