MOSFET Short-Channel Effects: DIBL, Velocity Saturation

As MOSFET channel lengths shrink below roughly 1 µm, the simple long-channel square-law model stops predicting real device behavior. Threshold voltage starts depending on drain voltage, drive current stops scaling as V², and output resistance collapses. These "short-channel effects" aren't exotic corner cases — they dominate the electrical behavior of every advanced-node MOSFET you'll encounter in modern ICs, and they explain why simulated gm, ro, and Vt in a 28 nm or smaller process look nothing like the textbook long-channel equations. Two of the most consequential effects are drain-induced barrier lowering (DIBL) and velocity saturation.

Why Long-Channel Assumptions Break Down

The classic square-law model assumes:

• The channel is long enough that the electric field is essentially one-dimensional (gradual channel approximation) — the drain has negligible influence on the source-side barrier.
• Carrier velocity v scales linearly with the lateral electric field E: v = μ·E, with mobility μ constant.

Both assumptions require the channel length L to be large compared to the depletion width and to the field lengths over which carriers accelerate. When L shrinks into the tens-to-hundreds-of-nanometer range, the drain depletion region becomes a significant fraction of the total channel length, and the lateral field at the drain end becomes large enough (often >10⁴–10⁵ V/cm) that carrier velocity saturates well before mobility's linear regime would predict. Both breakdowns move drive current and output resistance away from long-channel predictions — usually in ways that hurt gain and increase leakage.

Drain-Induced Barrier Lowering (DIBL)

Mechanism. In a long-channel device, the source-side potential barrier that carriers must overcome to enter the channel is set almost entirely by the gate voltage. In a short-channel device, the source and drain depletion regions are close enough together that the drain's electric field reaches back and lowers this barrier directly — independent of the gate. A higher VDS pulls the barrier down further, making it easier for carriers to be injected from the source.

Effect on threshold voltage. The practical consequence is a threshold voltage that decreases with increasing drain voltage:

Vt(VDS) = Vt0 − λ_DIBL·VDS

where λ_DIBL is an empirical DIBL coefficient (units of V/V, typically tens to hundreds of mV per volt of VDS in scaled nodes). Because Vt drops as VDS rises, subthreshold and saturation currents both increase with VDS even after the channel is nominally "pinched off" — this shows up directly as excess output conductance.

Why it matters for circuit design:

• Output resistance degradation: ro = 1/(∂ID/∂VDS) shrinks because ID now has an explicit VDS dependence through Vt, on top of channel-length modulation — reducing intrinsic gain gm·ro, a major reason cascoding and gain-boosting are near-mandatory in scaled-node analog design.
• Subthreshold leakage: DIBL raises off-state (VGS = 0) leakage because the effective threshold at high VDS is lower than at VDS ≈ 0 — a direct contributor to static power in digital ICs with long stacks of series transistors held at high VDS.
• Short-channel Vt roll-off: DIBL compounds with charge-sharing threshold roll-off, making Vt a strong function of both L and VDS — a matching and PVT-corner concern in low-voltage analog design.

Velocity Saturation

Mechanism. The long-channel drift model v = μ·E predicts unbounded velocity as E grows. Real carriers cannot exceed a saturation velocity v_sat (silicon electrons: roughly 1×10⁷ cm/s) because increasing field energy is transferred to phonon scattering rather than further acceleration. A practical empirical model:

v(E) = μ·E / (1 + E/E_c)      (electrons, single-parameter fit)

where E_c ≈ 2·v_sat/μ is the critical field at which the extrapolated unsaturated velocity μ·E_c would equal 2·v_sat; substituting E = E_c into the formula above gives v(E_c) = v_sat, i.e. the carrier velocity reaches the full asymptotic saturation velocity at that field. In short-channel devices, the lateral field E ≈ VDS/L (or more precisely the field at the drain end of the channel) reaches E_c at modest VDS because L is small, so velocity saturation is engaged well before the classical pinch-off condition VDS = VGS − Vt is reached.

Effect on drive current. The long-channel saturation current scales quadratically:

ID_longchannel = (μ·Cox/2)·(W/L)·(VGS − Vt)²

Once velocity saturation dominates, current instead approaches a linear dependence on (VGS − Vt), because carriers move at a fixed v_sat regardless of how much higher the field pushes:

ID_satvel ≈ W·Cox·v_sat·(VGS − Vt)          (fully velocity-saturated limit)

A widely used interpolation (Sodini/Toriumi-style unified model) captures both regimes:

ID ≈ (μ·Cox/2)·(W/L)·(VGS − Vt)² / [1 + (VGS − Vt)/(E_c·L)]

which reduces to the square law when (VGS−Vt)/(E_c·L) ≪ 1 and to the linear form when it dominates.

Why it matters for circuit design:

• Reduced transconductance efficiency: Because ID grows linearly rather than quadratically with VGS − Vt, gm becomes roughly constant rather than proportional to overdrive — gm/ID at a given overdrive is lower than square-law predicts, changing bias-point tradeoffs for low-power analog design.
• Reduced switching current benefit from scaling: Digital designers scaling L for speed get less current improvement than 1/L would suggest, since velocity-saturated current no longer benefits from shorter channel the way square-law current does.
• Interaction with DIBL: Both effects push real behavior toward a device that looks resistor-like sooner with worse output resistance than long-channel theory predicts — why SPICE models beyond Level 1/2 (BSIM3/4, PSP, etc.) are mandatory for short-channel design.

Worked Comparison: Long-Channel vs. Short-Channel Prediction

Assume W/L = 10, Cox = 10 fF/µm², μ = 300 cm²/V·s, Vt0 = 0.4 V, VGS = 1.0 V (overdrive VGS−Vt0 = 0.6 V), VDS = 1.0 V, L = 40 nm, v_sat = 1×10⁷ cm/s.

Step 1 — long-channel square-law estimate:

ID = (μ·Cox/2)·(W/L)·(VGS−Vt)²
   = (300 cm²/Vs · 10 fF/µm² / 2) · 10 · (0.6 V)²

In practice designers pull kn' = μ·Cox directly from a PDK; taking kn' ≈ 300 µA/V² as consistent with the given μ and Cox magnitude:

ID ≈ (300 µA/V² / 2) · 10 · 0.36 V² = 540 µA

Step 2 — check whether velocity saturation applies: Critical field E_c = 2·v_sat/μ. With μ = 300 cm²/Vs and v_sat = 1×10⁷ cm/s:

E_c = 2×10⁷ / 300 ≈ 6.7×10⁴ V/cm = 6.7 V/µm

Field at drain end ≈ VDS/L = 1.0 V / 0.04 µm = 25 V/µm, which is well above E_c (25 vs. 6.7 V/µm) — confirming this device is deep into velocity saturation, so the square-law estimate above is not physically valid.

Step 3 — velocity-saturated estimate:

ID_satvel = W·Cox·v_sat·(VGS−Vt)

With W = 10·L = 0.4 µm, Cox = 10 fF/µm² = 1×10⁻⁶ F/cm², v_sat = 1×10⁷ cm/s, (VGS−Vt) = 0.6 V:

ID ≈ 0.4×10⁻⁴ cm · 1×10⁻⁶ F/cm² · 1×10⁷ cm/s · 0.6 V
   ≈ 2.4×10⁻⁴ A ≈ 240 µA

Check: 240 µA (velocity-saturated) vs. 540 µA (naive square-law) — roughly 2.25× lower, consistent with velocity saturation suppressing drive current well below the quadratic prediction once E ≫ E_c. This gap is why SPICE-verified currents, not hand square-law math, must drive real transistor sizing at sub-100 nm-equivalent overdrives.

Practical Design Implications

Key Takeaways

• DIBL lowers the effective threshold voltage as VDS increases (Vt = Vt0 − λ_DIBL·VDS), because the drain field reaches back and reduces the source-side barrier — this degrades output resistance and raises off-state leakage.
• Velocity saturation caps carrier velocity at v_sat once the lateral field approaches the critical field E_c = 2v_sat/μ, causing drive current to trend from quadratic toward linear in (VGS − Vt) as channel length shrinks.
• Both effects reduce intrinsic gain (gm·ro) and drive current below long-channel square-law predictions — cascoding, gain-boosting, and careful VDS-dependent biasing become standard mitigations in analog design.
• A quick check — compare VDS/L to E_c — tells you immediately whether a device is in the square-law or velocity-saturated regime before trusting any hand calculation.
• For any sub-µm node, rely on BSIM3/4, PSP, or foundry-supplied compact models in SPICE rather than the long-channel square-law equation for quantitative sizing; use hand equations only for order-of-magnitude sanity checks.