MOSFET Small-Signal Model: gm, gds, Cgs, Cgd

Every MOSFET amplifier, RF stage, or switching regulator control loop is ultimately analyzed by replacing the transistor with a small-signal equivalent circuit valid around a DC operating point. Getting gm, gds, Cgs, and Cgd right — and knowing which ones dominate at a given frequency — is what separates a hand calculation that predicts real bandwidth and gain from one that's off by an order of magnitude.

Why Small-Signal Models Exist

A MOSFET's large-signal I-V behavior is nonlinear: ID = f(VGS, VDS) involves square-law or velocity-saturated terms. For small perturbations around a bias point (Q-point), this nonlinear function can be linearized using a first-order Taylor expansion. The result is a linear circuit — resistors, capacitors, and a dependent current source — that's valid only for small vgs, vds excursions around that Q-point, but is enormously easier to analyze with superposition, phasors, and standard circuit theorems.

The four parameters gm, gds, Cgs, Cgd are the minimum set needed to capture gain and frequency response for a single MOSFET in saturation.

Transconductance: gm

gm relates a small change in gate-source voltage to a small change in drain current, at constant VDS:

gm = ∂ID/∂VGS |VDS const

For a long-channel MOSFET in saturation, ID = (k'/2)(W/L)(VGS − VT)²(1 + λVDS). Differentiating (ignoring the λVDS term for the DC value):

gm = k'(W/L)(VGS − VT) = √(2·k'·(W/L)·ID)

Two equivalent forms are useful depending on what's known:

This is the current source in the small-signal model: id = gm·vgs. It sets the intrinsic voltage gain of the stage — for a simple common-source amplifier with drain resistor RD, gain magnitude is gm·RD (ignoring gds).

Design implication: for fixed ID, a larger W/L gives higher gm but at the cost of larger gate capacitance (see below) — a direct area/bandwidth/power trade-off that recurs throughout analog and RF MOSFET design.

Output Conductance: gds

gds (or its reciprocal, ro = 1/gds) models the finite slope of the ID vs. VDS curve in saturation — ideally flat, but real devices show a slight upward slope due to channel-length modulation:

gds = ∂ID/∂VDS |VGS const = λ·ID   (using ID·λ as the small-signal approximation)
ro = 1/gds = 1/(λ·ID) ≈ VE / ID   (VE = 1/λ, analogous to BJT's VA)

ro appears in parallel with the current source gm·vgs and with any external drain load. It caps the maximum achievable intrinsic gain of a single transistor:

Av,max = gm·ro   (intrinsic/self-gain, no external load)

For short-channel devices, λ is larger (shorter channel → stronger channel-length modulation and additional short-channel effects such as DIBL), so ro is lower and intrinsic gain drops — one reason cascoding and multi-stage topologies matter more as processes scale down.

Gate Capacitances: Cgs and Cgd

The gate forms a MOS capacitor with the channel and overlaps with the source/drain regions. Two capacitances dominate the small-signal high-frequency behavior:

• Cgs — gate-to-source capacitance, dominated by the gate-oxide capacitance over the channel (roughly (2/3)·Cox·W·L in saturation, from distributed channel-charge partitioning) plus a smaller gate-source overlap term.
• Cgd — gate-to-drain capacitance, almost entirely gate-drain overlap capacitance in saturation (the channel pinches off near the drain, so the intrinsic component is small). It's much smaller than Cgs in absolute terms, but its effect is amplified by the Miller effect.

Cox = εox / tox   (oxide capacitance per unit area)
Cgs ≈ (2/3)·Cox·W·L + CGSO·W     (channel term + overlap term)
Cgd ≈ CGDO·W                      (overlap term dominates in saturation)

Miller effect: in a common-source stage with gain −Av from drain to gate, Cgd is seen from the gate side as an effective capacitance of Cgd·(1 + Av). This is usually the dominant capacitance limiting bandwidth in an inverting voltage-gain stage, even though Cgd itself is the smaller physical capacitor.

The Complete Small-Signal Model

        Cgd
   G ────||────┐
   │           │
  Cgs          gm·vgs      ro (=1/gds)
   │           │  │           │
   S ──────────┴──┴───────────┘
                D

Equivalent description: a voltage-controlled current source id = gm·vgs from drain to source, in parallel with ro, plus Cgs from gate to source and Cgd from gate to drain. Body effect (gmb) is often added for accuracy in IC design but is neglected here for a discrete/first-pass model.

Worked Example

NMOS in saturation: ID = 2 mA, VOV = VGS − VT = 0.2 V, λ = 0.05 V⁻¹, Cgs = 0.4 pF, Cgd = 0.08 pF, driving a common-source stage with RD = 5 kΩ and source grounded.

Step 1 — gm:

gm = 2·ID/VOV = 2·(2mA)/0.2V = 20 mA/V = 20 mS

Step 2 — ro and gds:

ro = 1/(λ·ID) = 1/(0.05 · 2mA) = 1/(0.1 mA/V) = 10 kΩ
gds = 1/ro = 0.1 mA/V = 100 µS

Step 3 — mid-band voltage gain (RD parallel with ro):

Rout = RD ‖ ro = (5k · 10k)/(5k + 10k) = 50000/15 = 3.33 kΩ
Av = −gm·Rout = −(20 mS)(3.33 kΩ) = −66.7 V/V

Step 4 — Miller-equivalent input capacitance:

Cgd,Miller = Cgd·(1 + |Av|) = 0.08 pF · (1 + 66.7) = 0.08 · 67.7 ≈ 5.42 pF
Cin,total = Cgs + Cgd,Miller = 0.4 pF + 5.42 pF ≈ 5.82 pF

Step 5 — dominant pole from source resistance Rs (assume Rs = 1 kΩ source drive impedance):

f_-3dB ≈ 1/(2π·Rs·Cin,total) = 1/(2π · 1kΩ · 5.82pF) ≈ 27.3 MHz

Check: Av = −66.7 is a reasonable mid-band gain for gm·Rout with these values (order of magnitude: 20 mS × 3.3 kΩ ≈ 66, matches). Cgd's physical value (0.08 pF) is 5× smaller than Cgs, yet after the Miller multiplication it becomes the dominant capacitance (5.42 pF vs 0.4 pF) — confirming the Miller effect claim and showing why Cgd and stage gain both need to be controlled to preserve bandwidth.

Practical Design Implications

• Biasing sets gm and ro: both scale with ID and VOV in opposite ways — raising ID raises gm but also raises gds (lowers ro), so gain (gm·ro) doesn't simply improve with more current; it depends on the process's VE = 1/λ.
• Cascoding: adding a cascode transistor boosts effective output resistance without touching gm, directly increasing achievable gain — a standard fix for the limited intrinsic gm·ro of short-channel devices.
• Bandwidth vs. gain trade-off: the same Cgd that couples feedback for stability also creates the Miller pole; low-gain or cascode stages reduce Miller multiplication and extend bandwidth.
• fT estimate: the unity-current-gain frequency uses these same parameters, fT ≈ gm / (2π·(Cgs + Cgd)), giving a quick figure of merit for how fast a device can be before this small-signal model itself starts to need higher-order refinement (e.g., substrate/body capacitances, gate resistance).
• Datasheet reality: manufacturers rarely publish gm, Cgs, Cgd directly for power/switching MOSFETs; instead they give Ciss, Coss, Crss (input, output, reverse-transfer capacitance) measured at a bias point, from which Cgd ≈ Crss and Cgs ≈ Ciss − Crss.

Key Takeaways

• gm = ∂ID/∂VGS is the transconductance driving the dependent current source id = gm·vgs; typical forms are gm = 2ID/VOV or gm = √(2k'(W/L)ID).
• gds = 1/ro = λ·ID models channel-length modulation; it caps the intrinsic gain of a single stage at gm·ro.
• Cgs is dominated by the gate-oxide channel capacitance (~2/3 Cox·W·L); Cgd is dominated by gate-drain overlap capacitance and is physically small but critically important via the Miller effect.
• The Miller effect multiplies Cgd by (1 + |Av|) as seen from the input, often making it the dominant bandwidth-limiting capacitance even though Cgs is physically larger.
• Datasheet Ciss/Coss/Crss map to these small-signal capacitances and are the practical entry point for real-device bandwidth and switching-speed estimates.