JFET: N-Channel and P-Channel, Pinch-Off Voltage

Junction Field-Effect Transistors (JFETs) show up wherever a designer needs a high-input-impedance, low-noise front end without the gate-oxide fragility of a MOSFET — electrometer amplifiers, photodiode transimpedance stages, guitar pedal preamps, and voltage-controlled resistors in AGC loops. Unlike a BJT, a JFET is controlled by an electric field across a reverse-biased junction rather than by injected base current, and unlike a MOSFET, that junction is a p-n diode, not an insulated gate. Understanding pinch-off is the key to predicting its DC operating point and its use as a square-law device.

Structure: N-Channel and P-Channel

A JFET is built from a bar of lightly doped semiconductor (the channel) with a heavily doped region of the opposite type diffused into it to form the gate. Current flows through the channel between two ohmic contacts called the source and drain; the gate-channel junction is normally kept reverse-biased so no significant gate current flows.

Symbol convention: the gate arrow points into the device for N-channel (like an NPN base arrow analog) and out for P-channel. Because the channel is a continuous piece of doped silicon present at zero gate bias, a JFET is a normally-on, depletion-mode device — it conducts with VGS = 0 and is progressively shut off as reverse bias increases. This is the opposite default state from an enhancement-mode MOSFET, which is normally off.

Why Reverse Bias Narrows the Channel

The gate-channel p-n junction behaves like any other junction: reverse bias widens its depletion region. Because the gate surrounds (or borders) the channel, that depletion region eats into the conductive channel from both sides (in a symmetric double-gate structure) or from one side, reducing the cross-sectional area available for current flow.

For an N-channel device, the gate is p-type and the channel is n-type. Applying VGS < 0 reverse-biases this junction. As |VGS| increases, the depletion region widens and the neutral channel thickness shrinks. At a specific voltage — the pinch-off voltage VP (also written VGS(off)) — the depletion regions from both sides meet at the channel's center, and the conductive path is fully depleted.

Critically, "pinch-off" does not mean current stops. It means the channel opening has been squeezed to (ideally) zero at one point along its length, which caps the current at a saturation value rather than shutting it off — analogous to fluid flow through a collapsing but not fully closed pipe under increasing back-pressure.

Pinch-Off Along the Channel vs. Pinch-Off Voltage — Two Related Uses

The term "pinch-off" appears in two contexts that are easy to conflate:

1. VGS(off) / VP — the gate-source voltage at which the channel is fully depleted with VDS ≈ 0. Below this (in magnitude), the JFET is cut off — no channel exists anywhere.
2. Pinch-off point along the channel at a given VGS — as VDS increases from zero, the channel is not uniformly biased: the drain end sees a larger effective reverse bias (VGD = VGS − VDS) than the source end. When VDS reaches VGS − VP (i.e., the drain-end local depletion reaches full pinch-off while the source end is still open), the channel pinches off at the drain end only. Beyond this VDS, further increases mostly drop across the depleted pinch-off region near the drain, and drain current saturates — this is the boundary between the triode (ohmic) and saturation (active) regions.

I-V Characteristics

Triode (ohmic) region — VDS < VGS − VP (channel open along its full length, JFET behaves as a voltage-controlled resistor):

ID ≈ IDSS · [2·(1 − VGS/VP)·(VDS/|VP|) − (VDS/VP)²]     (N-channel, VP < 0)

Saturation (active) region — VDS ≥ VGS − VP, drain current is essentially independent of VDS (ignoring channel-length modulation) and follows the Shockley square-law:

ID = IDSS · (1 − VGS/VP)²         for VP < VGS < 0   (N-channel)

• IDSS — drain current with VGS = 0, VDS large enough for saturation (the maximum current the device can carry).
• VP (VGS(off)) — gate-source voltage at which ID → 0; negative for N-channel, positive for P-channel.
• The square-law shape (not linear, not exponential) is what distinguishes JFET/MOSFET transconductance behavior from BJT's exponential law and gives JFETs their favorable low-distortion, voltage-controlled-resistor behavior in triode.

Cutoff — VGS beyond VP in the reverse direction (more negative than VP for N-channel): channel fully depleted everywhere, ID ≈ 0 regardless of VDS.

Worked Example

A 2N-type N-channel JFET has IDSS = 8 mA and VP = −4 V. Find ID at VGS = −2 V, and determine the minimum VDS for saturation.

Step 1 — Saturation current:

ID = IDSS·(1 − VGS/VP)² = 8 mA·(1 − (−2)/(−4))² = 8 mA·(1 − 0.5)² = 8 mA·0.25 = 2 mA

Step 2 — Boundary VDS for onset of saturation:

VDS(sat) = VGS − VP = −2 − (−4) = 2 V

So for any VDS ≥ 2 V, ID stays at ≈ 2 mA (ignoring ro effects).

Check: At VGS = 0, the formula should return IDSS: ID = 8 mA·(1 − 0)² = 8 mA ✓. At VGS = VP = −4 V, ID = 8 mA·(1 − 1)² = 0 ✓, confirming cutoff at pinch-off voltage as expected. The result at −2 V (halfway to VP) giving IDSS/4 rather than IDSS/2 is consistent with the square-law (not linear) dependence — a useful sanity check when hand-estimating bias points.

Transconductance and Small-Signal Use

Differentiating the saturation equation gives the small-signal transconductance:

gm = ∂ID/∂VGS = −(2·IDSS/VP)·(1 − VGS/VP) = 2·IDSS/|VP| · √(ID/IDSS)

For the example above: gm = 2·8mA/4V · √(2/8) = 4 mA/V · 0.5 = 2 mA/V. This sets the voltage gain of a common-source stage (Av ≈ −gm·RD) exactly as it would for a MOSFET — the small-signal models are structurally identical once biased, differing mainly in how the gate is biased (through a resistor to ground is fine for a JFET since gate current is a reverse-junction leakage in the pA–nA range, not zero as assumed ideally, but still far higher input impedance than a BJT's base).

Practical Design Implications

• Self-bias is the standard DC bias scheme: a source resistor RS sets VGS = −ID·RS (N-channel) automatically, using the fact that gate current is negligible so the gate can sit at 0 V through a large resistor to ground.
• Depletion-mode default-on behavior makes JFETs useful as current limiters and voltage-controlled resistors (VDS/ID ratio in triode) without needing a positive gate drive.
• Wide VP and IDSS spread between devices of the same part number (often 3:1 or more) is normal — self-bias designs are chosen specifically because they tolerate this spread better than fixed-bias schemes.
• Gate must never be forward-biased into the channel junction beyond the diode's turn-on voltage, or gate current flows and control is lost; this bounds the usable VGS range on the opposite side from VP.
• Low noise and high ZIN make JFETs the front-end device of choice in electrometers, pH probes, and photodiode preamps where BJT base current or MOSFET gate leakage/1/f noise would dominate.

Key Takeaways

• JFETs are depletion-mode, normally-on devices controlled by reverse-biasing the gate-channel junction; N-channel uses negative VGS, P-channel uses positive VGS.
• Pinch-off voltage VP (VGS(off)) is the gate bias at which the channel is fully depleted and ID → 0; it does not mean the device physically stops conducting under all conditions — it's a boundary condition of the depletion geometry.
• Along the channel at a given VGS, local pinch-off near the drain (when VDS = VGS − VP) marks the triode-to-saturation boundary, not full device cutoff.
• Saturation current follows Shockley's square law, ID = IDSS·(1 − VGS/VP)², distinct from the BJT's exponential law.
• Self-bias networks are the standard way to accommodate the large IDSS/VP spread between individual JFETs of the same part number.