Early Effect: VA, Output Resistance (ro) in BJT

In an ideal BJT model, collector current in the active region depends only on V_BE and is completely independent of V_CE. Real transistors violate this: the collector current keeps rising slightly as V_CE increases, even with V_BE (and hence I_B) held fixed. This is the Early effect, and the finite slope it produces sets the output resistance ro of the transistor — a parameter that directly limits the voltage gain of every single-transistor amplifier stage and every current mirror you'll design.

Physical Origin

The base-collector junction is reverse-biased in the active region, and like any reverse-biased junction it has a depletion region whose width grows with reverse voltage. As V_CE (and therefore V_CB) increases, the base-collector depletion region widens, encroaching further into the base.

The base is physically thin (fractions of a µm in modern devices), so this widening measurably shrinks the effective neutral base width W_B. A narrower base means:

• A steeper minority-carrier concentration gradient across the base for the same V_BE (since the gradient is (n_B0·(e^(V_BE/V_T) − 1))/W_B).
• A steeper gradient means more carriers diffuse across per unit time → higher collector current.

So I_C increases with V_CE not because of any change in the emitter-base injection mechanism, but because the effective base width is being modulated by the collector voltage. This is why the effect is often called base-width modulation.

The VA Model

Empirically and to first order, the extra current tracks linearly with V_CE, so the collector current in the forward-active region is modeled as:

I_C = I_S·(e^(V_BE/V_T) − 1)·(1 + V_CE/V_A)

V_A is the Early voltage — a device parameter (typically 20 V to 200 V for discrete/IC BJTs) that quantifies how strongly V_CE modulates I_C. A larger V_A means less base-width modulation, i.e., a more ideal transistor.

Key geometric property: if you plot the I_C–V_CE family of curves (one curve per I_B, the classic BJT characteristic curves) and extend the straight-line active-region segments backward, they all converge at a single point on the negative V_CE axis: V_CE = −V_A. This extrapolation is the standard way V_A is extracted from measured or simulated curves — you don't need to bias the device into breakdown to find it.

 I_C
  │        /│  /│  /│   (increasing I_B)
  │       / │ / │ / │
  │      /  │/  │/  │
  │     /   /   /   /
  │    /   /|  /|  /|
  │   /   / | / | / |
  │  /   /  |/  |/  |
  │ /   /   /   /   /
  ├────┴────┴────┴────┴──── V_CE
 −V_A  0

Output Resistance ro

The small-signal output resistance looking into the collector, at a fixed operating point, is defined as:

ro = ∂V_CE / ∂I_C  (at constant V_BE, I_B, or I_E — depending on model context)

Differentiating the I_C expression with respect to V_CE (treating I_S·(e^(V_BE/V_T)−1) as the DC value I_C0 at V_CE = 0, and using the fact that V_A is much larger than typical V_CE so I_C ≈ I_C0):

ro ≈ (V_A + V_CE) / I_C ≈ V_A / I_C

The approximation ro ≈ V_A/I_C (dropping V_CE relative to V_A) is the one used in virtually all hand analysis, and it appears directly as the collector-emitter resistance in the hybrid-π small-signal model, in parallel with the dependent current source gm·v_be.

Worked Example

A BJT is biased at I_C = 1 mA and has a datasheet/SPICE-model Early voltage V_A = 100 V. Find ro, and find the maximum voltage gain (the intrinsic gain) achievable in a common-emitter stage using this device alone as a current source load.

Step 1 — output resistance:

ro ≈ V_A / I_C = 100 V / 1 mA = 100 kΩ

Step 2 — transconductance:

gm = I_C / V_T = 1 mA / 25.9 mV ≈ 38.6 mA/V

Step 3 — intrinsic gain (the gain of a common-emitter stage with an ideal current-source collector load, limited only by the transistor's own ro):

|Av,max| = gm·ro = (I_C/V_T)·(V_A/I_C) = V_A/V_T = 100 V / 0.0259 V ≈ 3861

Check: Note V_A/V_T is independent of bias current — both gm and ro scale inversely and directly with I_C respectively, so their product only depends on V_A and V_T. Sanity check the magnitude: 3861 ≈ 71.7 dB, consistent with the well-known rule of thumb that a single BJT stage's intrinsic gain is in the thousands, not the millions — this is exactly why cascoding and multi-stage topologies exist in op-amp design.

Why This Matters in Real Circuits

1. Current mirrors. An ideal mirror produces two perfectly matched, V_CE-independent output currents. With finite ro, the output current of a simple mirror depends on the output-branch V_CE:

ΔI_out/I_out ≈ ΔV_CE / V_A

For V_A = 50 V and a 1 V swing at the output node, the current shifts by 1/50 = 2% — often unacceptable in precision analog blocks, motivating cascode current mirrors that boost effective output resistance by roughly a factor of gm·ro of the cascode device.

2. Voltage gain limits. Every single-stage BJT amplifier's maximum achievable gain is bounded by gm·ro = V_A/V_T, regardless of how the load is chosen (a truly ideal infinite-impedance load just reduces to this limit). Real resistive loads always give less.

3. Small-signal model placement. In the hybrid-π model, ro connects collector to emitter, in parallel with gm·v_be. It's usually the largest resistance in the small-signal circuit, so it's often neglected when the external load is much smaller — but it cannot be neglected in cascode stages, active-load differential pairs, or any node with high external impedance.

4. Process and geometry dependence. V_A depends on base doping profile and base width — it's a device/process parameter, not something a circuit designer tunes directly, though transistor sizing (multiple emitter fingers, geometry) and bias current selection do affect the effective V_A seen in the model, especially in modern IC BJTs where V_A can drop at very high or very low I_C.

Comparison with the MOSFET Analog

The mathematical form is identical, which is why the same cascode and current-mirror tricks used in bipolar design carry over directly to MOSFET design.

Key Takeaways

• The Early effect is base-width modulation: increasing V_CE widens the base-collector depletion region, narrows the effective base, and steepens the diffusion gradient, raising I_C.
• The model I_C = I_S·(e^(V_BE/V_T)−1)·(1 + V_CE/V_A) captures this with one parameter, the Early voltage V_A, typically 20–200 V.
• Extrapolating the linear active-region I_C–V_CE curves back to the V_CE axis gives −V_A — the standard extraction method.
• Output resistance ro ≈ V_A/I_C sits between collector and emitter in the hybrid-π model and sets the upper bound on single-stage gain via gm·ro = V_A/V_T.
• Finite ro degrades current-mirror accuracy (ΔI/I ≈ ΔV_CE/V_A) and caps amplifier gain — the reasons cascode topologies and multi-stage designs exist.