Transmission Line Theory: Characteristic Impedance Z0

At DC and low frequencies, a wire is just a wire — connect two points and the voltage is the same everywhere along it. That assumption breaks down once the interconnect is no longer short compared with the signal's wavelength, or, for digital signals, once the line's propagation delay becomes comparable to the edge rise time. For edges just under a nanosecond that means traces a few centimeters long; for 100 ps edges, only a few millimeters. Beyond that point the conductor must be treated as a transmission line, and its behavior is governed by a single defining parameter: characteristic impedance, Z0.

Why Wires Stop Being "Just Wires"

A physical conductor pair — a trace over a ground plane, a coax cable, a twisted pair — has distributed inductance and capacitance along its length, not lumped values at one point. A signal edge propagates as an electromagnetic wave along this structure, and for a wave traveling in one direction the ratio of voltage to current is fixed by the line's geometry and materials. That ratio is Z0. When reflections are present, the total voltage-to-current ratio varies along the line, but each traveling wave still obeys Z0.

The practical rule for when this matters marks the boundary between lumped and distributed element circuits: treat an interconnect as a transmission line when its one-way propagation delay exceeds about one-sixth of the signal's rise time. Once the round-trip delay exceeds the rise time, reflections show up as separate steps on the edge and termination is no longer optional. In frequency terms, an edge with rise time t_r carries significant energy up to about 0.35/t_r, and a line longer than roughly 1/10 of the wavelength at that frequency behaves as a transmission line.

For a 100 ps edge on FR4 (about 15 cm/ns, roughly 6 in/ns):

Lumped limit, delay = t_r/6 = 16.7 ps      →  ≈ 2.5 mm
λ/10 at 0.35/t_r = 3.5 GHz                 →  ≈ 4.3 mm
Round trip = t_r, delay = t_r/2 = 50 ps    →  ≈ 7.5 mm

All three are well within ordinary PCB dimensions.

The Distributed Model

A transmission line is modeled as an infinite cascade of infinitesimal sections, each described by per-unit-length parameters. The lossless LC version is drawn below; in the lossy model, R'dx sits in series with each inductor and G'dx in parallel with each capacitor.

o---[L'dx]---+---[L'dx]---+---[L'dx]---+---o
             |            |            |
           C'dx         C'dx         C'dx
             |            |            |
o------------+------------+------------+---o

• L' — inductance per unit length (H/m)
• C' — capacitance per unit length (F/m)
• R' — series resistance per unit length (Ω/m, conductor loss)
• G' — shunt conductance per unit length (S/m, dielectric loss)

For the lossless line (R' = G' = 0, the standard first approximation for short PCB traces at moderate frequency):

Z0   = √(L'/C')                  [purely real, in ohms]
v_p  = 1/√(L'·C') = c/√εr,eff    [propagation velocity]
t_pd = √(L'·C')                  [delay per unit length]

Z0 is not a resistor. A lossless line dissipates no power, yet until a reflection returns, the driver sees the line as a resistance of Z0 and delivers real power into it — power that travels down the line instead of turning into heat. Z0 is the ratio of the traveling voltage wave to its traveling current wave at any point on the line. Doubling the line length doubles total L and total C but leaves L'/C' — and hence Z0 — unchanged. This is the key conceptual difference from a discrete resistor.

For the general lossy line, Z0 is complex and frequency-dependent (see phasor representation and complex impedance):

Z0 = √[(R' + jωL') / (G' + jωC')]

At high enough frequency (ωL' ≫ R' and ωC' ≫ G'), this collapses back to the lossless √(L'/C') result. For typical PCB traces that holds from roughly 10–20 MHz upward, which covers most digital edges and RF signals, and it is why Z0 = √(L'/C') is used almost universally in signal integrity work. The losses don't disappear, though: R' keeps rising with frequency because of the skin effect, and G' grows with frequency too, so they still set the line's attenuation even after they stop affecting Z0.

Typical Values and Geometry Dependence

Z0 depends only on cross-sectional geometry and dielectric — not on line length. Common target values and their typical realizations:

For a microstrip over a ground plane, a widely used closed-form approximation (IPC-2141) is:

Z0 ≈ (87 / √(εr + 1.41)) · ln(5.98·h / (0.8·w + t))   [Ω]

where εr is the dielectric constant, h the dielectric height, w the trace width, and t the trace thickness (all in consistent units, e.g. mils). It is accurate to roughly ±5% for 0.1 < w/h < 2 and εr < 15; for production stack-ups, confirm with a field solver and the fabricator's impedance calculation. Example: a 0.35 mm trace in 1 oz copper (t ≈ 0.035 mm) over 0.2 mm of FR4 (εr ≈ 4.3) gives Z0 ≈ 49 Ω.

The practical takeaway: narrower traces and thicker dielectric raise Z0; wider traces, thinner dielectric, thicker copper, and higher εr lower it. This is why PCB designers control trace width and layer stack-up, not just copper thickness, to hit a 50 Ω target.

Worked Example: Finding Z0 from L' and C'

A stripline in FR4 (εr ≈ 4.7) is characterized by a field solver as having:

• L' = 3.6 nH/cm
• C' = 1.45 pF/cm

Step 1 — Characteristic impedance:

Z0 = √(L'/C') = √(3.6×10⁻⁹ / 1.45×10⁻¹²) = √(2483) ≈ 49.8 Ω

This is close to the 50 Ω target common in digital design.

Step 2 — Delay and propagation velocity:

t_pd = √(L'·C') = √(3.6×10⁻⁹ × 1.45×10⁻¹²) = √(5.22×10⁻²¹) ≈ 72 ps/cm   (≈ 183 ps/in)
v_p  = 1/t_pd ≈ 1.38×10¹⁰ cm/s = 1.38×10⁸ m/s   (≈ 0.46 c)

A 10 cm trace therefore has about 0.72 ns of delay — far beyond the lumped limit for any sub-nanosecond edge.

Step 3 — Sanity check against εr:

εr,eff = (c / v_p)² = (3×10⁸ / 1.38×10⁸)² ≈ 4.7

A stripline is fully embedded in a homogeneous dielectric, so its effective εr must equal the bulk εr of the laminate; there is no air-filled part of the field to lower it, as there is in microstrip. Here 4.7 matches FR4, so the L'/C' pair is physically consistent.

The same check catches bad data quickly. L' = 4.2 nH/cm and C' = 1.7 pF/cm also give Z0 ≈ 49.7 Ω, but imply εr,eff ≈ 6.4 — impossible for an FR4 stripline. For a given Z0 the ratio L'/C' is fixed; it is the product L'·C' that has to match the dielectric.

Why Z0 Matters: Reflections and Matching

The practical consequence of Z0 shows up at any impedance discontinuity — a connector, a via, or the termination at the far end of the line. When a traveling wave hits a load ZL that differs from Z0, part of the wave reflects:

Γ = (ZL − Z0) / (ZL + Z0)

• ZL = Z0 (matched): Γ = 0, no reflection, all incident energy absorbed by the load — the ideal case for high-speed digital and RF links.
• ZL = ∞ (open): Γ = +1, full reflection, same polarity.
• ZL = 0 (short): Γ = −1, full reflection, inverted polarity.
• ZL = 3·Z0, e.g. Z0 = 50 Ω, ZL = 150 Ω: Γ = (150−50)/(150+50) = 100/200 = 0.5 — 50% of the incident voltage, and 25% of the incident power, reflects back toward the source. As return loss, that is −20·log₁₀(0.5) ≈ 6 dB (see decibels for voltage and power ratios).

Unterminated or badly matched lines produce ringing, overshoot, and — on lines that are long relative to the rise time — visible steps or double edges on an oscilloscope, all traceable to Γ ≠ 0 at one or both ends. One mismatched end produces a single reflection; sustained ringing needs mismatches at both ends, so the wave keeps bouncing between them.

The fix is to match at least one end:

• Series (source) termination: a resistor at the driver so that R_driver + R_series ≈ Z0. The far-end reflection is absorbed when it returns to the source; standard for point-to-point links.
• Parallel (end) termination: R ≈ Z0 at the receiver, to ground or a termination voltage. No reflection, at the cost of DC current.
• AC termination: R ≈ Z0 in series with a capacitor at the receiver, which removes the DC load.
• Differential termination: about 100 Ω across the pair at the receiver, as in LVDS.

This is the direct link between Z0 and practical signal integrity: controlled-impedance PCB stack-ups exist specifically to keep Z0 predictable so terminations can be designed to match it.

Key Takeaways

• Characteristic impedance Z0 = √(L'/C') (lossless case) is the ratio of voltage to current in a wave traveling along a distributed line — a property of geometry and dielectric, independent of line length.
• Treat an interconnect as a transmission line once its delay exceeds about one-sixth of the edge rise time (≈ 2.5 mm for a 100 ps edge on FR4); once the round-trip delay exceeds the rise time, termination is mandatory.
• At high frequency the lossy Z0 approaches √(L'/C'), but R' and G' still set attenuation.
• Typical single-ended targets are 50 Ω (RF, digital) and 75 Ω (video); differential pairs commonly target 90–100 Ω.
• Trace geometry (width, dielectric height, εr) sets Z0; closed-form approximations like the IPC-2141 microstrip formula get you close, and a field solver confirms the stack-up.
• For a stripline, εr,eff = (c/v_p)² must equal the laminate's εr — a fast consistency check on L' and C' data.
• Any mismatch between ZL and Z0 produces a reflection coefficient Γ = (ZL − Z0)/(ZL + Z0) ≠ 0, causing ringing and signal integrity problems unless the line is properly terminated.