Transmission Line Theory: Characteristic Impedance Z0

At DC and low frequencies, a wire is just a wire — connect two points and the voltage is the same everywhere along it. That assumption breaks down the moment signal wavelength approaches the physical length of the interconnect, which for digital edges in the sub-nanosecond range means anything longer than a few centimeters. Once that happens, the conductor must be treated as a transmission line, and its behavior is governed by a single defining parameter: characteristic impedance, Z0.

Why Wires Stop Being "Just Wires"

A physical conductor pair — a trace over a ground plane, a coax cable, a twisted pair — has distributed inductance and capacitance along its length, not lumped values at one point. A signal edge propagates as an electromagnetic wave along this structure, and at every point along the line the local ratio of voltage to current is fixed by the line's geometry and materials. That ratio is Z0.

The rule of thumb for when this matters: treat an interconnect as a transmission line (distributed) rather than a lumped node when its length exceeds roughly 1/10 of the signal's electrical wavelength, or equivalently when the signal's rise time is comparable to or shorter than the line's propagation delay times ~2 (round trip). For a 100 ps rise-time digital edge and a trace with ~6 in/ns propagation velocity, that threshold is on the order of 1–2 cm — well within ordinary PCB dimensions.

The Distributed Model

A transmission line is modeled as an infinite cascade of infinitesimal LC sections, each representing per-unit-length parameters:

o---[L'dx]---+---[L'dx]---+---[L'dx]---+---o
             |            |            |
           C'dx         C'dx         C'dx
             |            |            |
o------------+------------+------------+---o

• L' — inductance per unit length (H/m)
• C' — capacitance per unit length (F/m)
• R' — series resistance per unit length (Ω/m, conductor loss)
• G' — shunt conductance per unit length (S/m, dielectric loss)

For the lossless line (R' = G' = 0, the standard first approximation for short PCB traces at moderate frequency):

Z0 = √(L'/C')          [purely real, in ohms]
v_p = 1/√(L'·C')        [propagation velocity]

Z0 is not a lumped resistance and dissipates no power — it's the ratio of the traveling voltage wave to its traveling current wave at any point on the line. Doubling the line length doubles total L and total C but leaves L'/C' — and hence Z0 — unchanged. This is the key conceptual difference from a discrete resistor.

For the general lossy line, the full expression includes frequency:

Z0 = √[(R' + jωL') / (G' + jωC')]

At high enough frequency (ωL' ≫ R' and ωC' ≫ G', true for most digital and RF signals above a few MHz on typical PCB traces), this collapses back to the lossless √(L'/C') result, which is why Z0 = √(L'/C') is used almost universally in signal integrity work.

Typical Values and Geometry Dependence

Z0 depends only on cross-sectional geometry and dielectric — not on line length. Common target values and their typical realizations:

For a microstrip over a ground plane, a widely used approximation (Wheeler/IPC-derived) is:

Z0 ≈ (87 / √(εr + 1.41)) · ln(5.98·h / (0.8·w + t))   [Ω]

where εr is the dielectric constant, h the dielectric height, w the trace width, t the trace thickness (all in consistent units, e.g. mils). The practical takeaway: narrower traces and thicker dielectric raise Z0; wider traces, thinner dielectric, thicker copper, and higher εr lower it. This is why PCB designers control trace width and layer stack-up, not just copper thickness, to hit a 50 Ω target.

Worked Example: Finding Z0 from L' and C'

A stripline is characterized (by field solver or measurement) as having:

• L' = 4.2 nH/cm
• C' = 1.7 pF/cm

Step 1 — Characteristic impedance:

Z0 = √(L'/C') = √(4.2×10⁻⁹ / 1.7×10⁻¹²) = √(2470.6) ≈ 49.7 Ω

This is close to the 50 Ω target common in digital design.

Step 2 — Propagation velocity:

v_p = 1/√(L'·C') = 1/√(4.2×10⁻⁹ × 1.7×10⁻¹² per cm²)
    = 1/√(7.14×10⁻²¹) = 1/(8.45×10⁻¹¹ s/cm)
    ≈ 1.183×10¹⁰ cm/s ≈ 1.18×10⁸ m/s

Step 3 — Sanity check against εr: effective εr ≈ (c/v_p)² = (3×10⁸ / 1.18×10⁸)² ≈ (2.54)² ≈ 6.5. Because a stripline is fully embedded in a homogeneous dielectric, its effective εr must equal the bulk dielectric εr exactly — there is no partial air-field fraction to lower it, unlike microstrip. Bulk FR4 εr is only ~4.3–4.8, so this L'/C' pair is not physically self-consistent with a real FR4 stripline; it was chosen purely to land Z0 near 50 Ω for the arithmetic. A stripline that actually sits in FR4 (εr ≈ 4.3–4.8) with Z0 = 50 Ω would need a smaller L'/C' ratio consistent with v_p = c/√εr ≈ 1.37–1.45×10⁸ m/s — e.g. L' ≈ 3.6 nH/cm and C' ≈ 1.45 pF/cm gives Z0 = √(3.6×10⁻⁹/1.45×10⁻¹²) ≈ 49.8 Ω with effective εr ≈ 4.70, within the stated FR4 range of 4.3–4.8.

Why Z0 Matters: Reflections and Matching

The practical consequence of Z0 shows up at any impedance discontinuity — a connector, a via, or the termination at the far end of the line. When a traveling wave hits a load ZL that differs from Z0, part of the wave reflects:

Γ = (ZL − Z0) / (ZL + Z0)

• ZL = Z0 (matched): Γ = 0, no reflection, all incident energy absorbed by the load — the ideal case for high-speed digital and RF links.
• ZL = ∞ (open): Γ = +1, full reflection, same polarity.
• ZL = 0 (short): Γ = −1, full reflection, inverted polarity.
• ZL = 3·Z0, e.g. Z0 = 50 Ω, ZL = 150 Ω: Γ = (150−50)/(150+50) = 100/200 = 0.5 — 50% of the incident voltage reflects back toward the source.

Unterminated or badly matched lines produce ringing, overshoot, and — on long enough lines relative to rise time — visible double-edges on an oscilloscope, all traceable to Γ ≠ 0 at one or both ends. This is the direct link between Z0 and practical signal integrity: controlled-impedance PCB stack-ups exist specifically to keep Z0 predictable so terminations can be designed to match it.

Key Takeaways

• Characteristic impedance Z0 = √(L'/C') (lossless case) is the ratio of traveling voltage to traveling current on a distributed line — a property of geometry and dielectric, independent of line length.
• Treat interconnects as transmission lines once length becomes a significant fraction of the signal's electrical wavelength or edge-related spatial extent — a common trigger for high-speed digital PCB traces.
• Typical single-ended targets are 50 Ω (RF, digital) and 75 Ω (video); differential pairs commonly target 90–100 Ω.
• Trace geometry (width, dielectric height, εr) sets Z0 via closed-form approximations like the microstrip formula — this is what PCB stack-up design controls.
• Any mismatch between load impedance ZL and Z0 produces a reflection coefficient Γ = (ZL−Z0)/(ZL+Z0) ≠ 0, causing ringing and signal integrity problems unless the line is properly terminated.