Difference Amplifier: CMRR and Resistor Matching

A difference amplifier subtracts two signals and rejects whatever they have in common — the classic use case is pulling a small differential signal (a bridge sensor, a shunt resistor, a line-driver receiver) out of a large common-mode background like ground bounce or 60 Hz pickup. The entire usefulness of the circuit hinges on one number: common-mode rejection ratio (CMRR), and CMRR in this topology is set almost entirely by how precisely four resistors are matched — not by the op-amp's own open-loop CMRR. Get the resistor ratios wrong by a fraction of a percent and the circuit's real-world rejection can be worse than a "poor" op-amp used in a non-inverting buffer.

Circuit and Transfer Function

The standard single op-amp difference amplifier:

        R2
   +----/\/\----+
   |            |
V1--/\/\--------+-----|-\
    R1                |  \
                       |   >----+---- Vout
              R3   +---|+ /     |
   V2--/\/\--+     |   |-/      |
       |      \-/\/\---+        
       |       R4                
      GND

More explicitly, with the standard labeling:

• V1 drives the inverting side through R1, with feedback resistor R2 from output to that same inverting node.
• V2 drives the non-inverting input through R3, which is then referenced to ground through R4.

For an ideal op-amp (infinite open-loop gain, infinite input impedance, zero Vos), superposition gives:

Vout = V2·[R4/(R3+R4)]·[(R1+R2)/R1] − V1·(R2/R1)

If the ratios are matched — R2/R1 = R4/R3 — this collapses to the familiar clean result:

Vout = (R2/R1)·(V2 − V1)

This is the textbook "difference amplifier" gain equation. Note it is not a differential amplifier with independently settable differential and common-mode gain — the input impedances seen by V1 and V2 are also unequal (R1 vs. R3+R4), which matters when driving it from finite-impedance sources. That limitation is exactly why the instrumentation amplifier (two additional buffer stages ahead of this same difference stage) exists as a separate topic — it fixes both the loading and the trim sensitivity problems.

Where CMRR Comes From

Apply a pure common-mode signal: V1 = V2 = Vcm. Ideally Vout = 0. In practice, any mismatch between the two resistor ratios leaves a residual common-mode-to-differential leakage.

Define the ratio mismatch. Let the nominal ratio be k = R2/R1 = R4/R3, but each resistor carries an independent tolerance ±ε (fractional, e.g. 0.01 for 1%). Worst case, the two ratios can differ by roughly:

Δ(ratio) ≈ 4ε      (worst-case, four resistors each off by ε in the worst direction)

The resulting common-mode gain and CMRR are approximately:

Acm ≈ k · Δ(ratio) / (1 + k)     [order-of-magnitude form]
CMRR ≈ Adiff / Acm ≈ (1 + k) / (4ε)

The key takeaways from this relation:

• CMRR degrades linearly with resistor tolerance. Halving ε doubles CMRR (in linear terms), i.e., adds about 6 dB.
• Higher gain (larger k) does not fix resistor-driven CMRR the way it might intuitively seem — the (1+k)/ε scaling means CMRR improves somewhat with gain, but tolerance dominates unless resistors are extremely well matched.
• The op-amp's own CMRR and open-loop gain add a separate, usually smaller, error term at DC/low frequency for a well-designed circuit with tight resistors — but at higher frequencies the op-amp's CMRR rolloff can dominate since resistor mismatch is frequency-independent while op-amp CMRR falls with frequency.

Worked Example

Design a difference amplifier with gain 10 (k = R2/R1 = R4/R3 = 10), using R1 = R3 = 10 kΩ, R2 = R4 = 100 kΩ, with standard 1% resistors (ε = 0.01).

Step 1 — nominal transfer function. Vout = 10·(V2 − V1), by design.

Step 2 — worst-case ratio mismatch. Each resistor can be off by ±1%. In the worst case, R2/R1 and R4/R3 diverge by up to:

Δ(ratio) ≈ 4 × 0.01 = 0.04   (4%)

Step 3 — approximate CMRR.

CMRR ≈ (1 + k)/Δ(ratio) = (1 + 10)/0.04 = 275 (linear)
CMRR(dB) = 20·log₁₀(275) ≈ 48.8 dB

Step 4 — translate to a real error. Suppose the common-mode voltage is 5 V (e.g., both inputs riding on a 5 V bias) and the true differential signal is 10 mV.

Ideal Vout = 10 × 0.010 V = 0.100 V
Common-mode-induced error ≈ Vcm / CMRR = 5 V / 275 ≈ 18.2 mV

That's an 18% error on a 100 mV expected signal — from resistor tolerance alone, with a perfect op-amp. This is why "just use a difference amp" often fails silently in sensor front ends: the math looks fine on paper, but 1% resistors turn a small differential signal riding on a large common-mode voltage into unreliable data.

Step 5 — check with tighter resistors. Switch to 0.1% resistors (ε = 0.001):

Δ(ratio) ≈ 4 × 0.001 = 0.004
CMRR ≈ 11/0.004 = 2750 (linear) ≈ 68.8 dB
Error ≈ 5 V / 2750 ≈ 1.8 mV   (1.8% of the 100 mV signal)

A 10× improvement in resistor tolerance buys roughly 20 dB of CMRR — consistent with the linear 1/ε scaling above, confirming the model.

Practical Design Techniques

Frequency Dependence

Resistor mismatch produces a CMRR limit that is essentially flat with frequency (resistors don't have significant frequency dependence at audio/instrumentation frequencies). The op-amp's own CMRR, however, rolls off with frequency — typically starting to degrade well below the gain-bandwidth product. The overall circuit CMRR is the more restrictive of the two at any given frequency:

• At DC/low frequency: resistor mismatch usually dominates (as shown above, tens of dB range for 0.1–1% resistors).
• At higher frequency: op-amp CMRR rolloff and any parasitic mismatch in stray capacitance to ground on the two input paths (which is rarely equal at R1 vs. R3+R4 nodes) can dominate, and cannot be fixed by resistor trimming alone.

Design Checklist

1. Decide the required CMRR from the expected common-mode voltage and the acceptable output error.
2. Solve ε ≈ (1+k) / (4·CMRR) for the maximum tolerable resistor mismatch.
3. Select resistor tolerance/matching accordingly — often a matched array rather than four discrete parts.
4. Verify with SPICE Monte Carlo (vary all four resistors within tolerance) rather than trusting the worst-case formula alone, since real distributions are rarely all-worst-case simultaneously.
5. If CMRR requirements exceed what discrete resistors can practically deliver (>80 dB), move to an integrated difference-amp IC or an instrumentation amplifier.

Key Takeaways

• The single op-amp difference amplifier's clean gain equation Vout = (R2/R1)(V2−V1) only holds when R2/R1 = R4/R3 exactly; any deviation creates common-mode-to-differential leakage.
• CMRR from resistor mismatch scales approximately as (1+k)/(4ε) — it degrades linearly with resistor tolerance ε, not merely as a rounding error.
• A 10× tighter resistor tolerance yields roughly 20 dB more CMRR; standard 1% resistors typically limit this topology to well under 60 dB CMRR.
• At low gain and DC, resistor mismatch usually dominates total CMRR; at higher frequency, op-amp CMRR rolloff and stray capacitance mismatch take over.
• For CMRR beyond what discrete matched resistors can reliably deliver, use a laser-trimmed integrated difference-amp IC or a full instrumentation amplifier front end instead of adding more trim resistors.