LTspice: Schematic Entry and Simulation Basics

Before a single prototype gets soldered, most analog and mixed-signal decisions — component values, stability margins, worst-case tolerances — get settled in SPICE. LTspice is the de facto free entry point for this: it's fast, has no node/component limits that matter for typical boards, and its convergence engine handles switching regulators and nonlinear devices better than most other free tools. Knowing how to build a clean schematic and set up the right analysis type is a prerequisite skill, not an optional extra, for every circuit covered in this roadmap.

What LTspice Actually Does

LTspice is a SPICE (Simulation Program with Integrated Circuit Emphasis) engine with a schematic capture front end. The workflow is always the same three steps:

1. Draw the circuit as a schematic (.asc file) using components from the library, or write a netlist directly.
2. Set up an analysis directive — DC operating point, DC sweep, AC sweep, or transient — as a SPICE command attached to the schematic.
3. Run the simulation; the engine builds a matrix of circuit equations (modified nodal analysis) and solves it numerically, then plots results in a waveform viewer.

Everything downstream (Bode plots, transient waveforms, worst-case Monte Carlo runs) is a consequence of getting these three steps right.

Schematic Entry: The Rules That Matter

A few conventions trip up newcomers and cause simulations to fail silently or give wrong answers:

• Every circuit needs a ground (node 0). SPICE solves for node voltages relative to ground; without a GND symbol placed somewhere, the simulation errors out or (worse) floats a subcircuit with no defined reference.
• Wires must actually connect. LTspice shows a solid dot at a true electrical junction. A wire crossing another wire without a dot is not connected — a common source of "circuit doesn't work" bugs.
• Component values use SPICE suffixes, not always what you'd expect: k = 10³, meg = 10⁶ (not M, which SPICE parses as milli), m = 10⁻³, u = 10⁻⁶, n = 10⁻⁹, p = 10⁻¹². Typing 1M for 1 MΩ is a classic error — SPICE reads it as 1 milliohm.
• Reference designators auto-increment (R1, R2, C1...) but are cosmetic; SPICE identifies nodes by wire connectivity, not by labels.
• Net labels let you connect nodes without drawing wires across a busy schematic — useful for feedback nets or bus signals, but easy to misspell and create an unintended open node.

Analysis Types and Their SPICE Directives

Each analysis is invoked with a . directive, entered via Simulate → Edit Simulation Cmd or typed directly as a SPICE directive text box on the schematic.

.ac requires linearizing the circuit around its DC operating point first — LTspice does this automatically, but it means any nonlinear element (diode, transistor) must have a valid bias point for the AC results to mean anything.

Worked Example: RC Low-Pass Step Response

Build a simple RC low-pass: R = 1 kΩ, C = 100 nF, driven from a voltage source producing a 0→1 V step at t = 0.

V1  in   0   PULSE(0 1 0 1n 1n 1m 2m)
R1  in   out 1k
C1  out  0   100n

Time constant: τ = RC = 1000 · 100n = 100 µs

For a step input, the analytical response is:

Vout(t) = Vfinal · (1 − e^(−t/τ))

At t = τ: Vout = 1·(1 − e⁻¹) = 1·(1 − 0.368) = 0.632 V At t = 5τ = 500 µs: Vout = 1·(1 − e⁻⁵) = 1·(1 − 0.0067) ≈ 0.993 V (settled to within 0.7%)

Simulation setup: .tran 1m (run for 1 ms, well past 5τ = 500 µs) with the PULSE source above. Running it in LTspice and probing node out should show the exponential rise crossing 0.632 V at t = 100 µs and flattening near 1 V by t = 500 µs — matching the hand calculation. If the simulated 63.2% point doesn't land at t = τ, the most common cause is a typo in the component suffix (e.g., 100u instead of 100n, which changes τ by 1000×) — always sanity-check the trace against the hand-calculated τ before trusting further results.

Check: at DC steady state (t → ∞), no current flows through C (open circuit for DC), so Vout = Vin = 1 V by the voltage divider with an open branch — consistent with the 0.993 V near-settled value above.

Reading Results: The Waveform Viewer

After a run, LTspice opens a plot pane automatically for .tran/.ac/.dc. Key operations:

• Click a wire or node in the schematic to add that voltage to the plot; click a component to probe its current.
• Right-click an axis to change scale (log frequency axis is essential for .ac results — this is exactly the log-frequency convention Bode plots depend on).
• Ctrl-click a trace to add a derived expression (e.g., power = V(out)*I(R1)), since the viewer supports arbitrary algebraic combinations of simulated signals.
• Add cursors to read exact values off a trace — critical for verifying τ, overshoot, or gain crossover numerically rather than by eye.

Practical Implications for Real Designs

• Initial conditions matter for transient analysis. A capacitor with unknown initial charge can show a spurious transient at t = 0; use .ic V(node)=value or let the simulator compute the DC operating point first (uic flag suppresses this if you deliberately want a specific starting state).
• Convergence issues are common with switching circuits. Loosening (increasing) .options reltol (or increasing gmin), or adding small parasitic resistances/capacitances, often resolves non-convergent DC solutions in circuits with ideal switches or steep nonlinearities — tightening reltol makes the convergence criterion stricter and typically makes convergence harder, not easier.
• Component models are only as good as the library. Free generic models (ideal op-amps, generic diodes) simulate cleanly but don't capture real parasitics — always substitute manufacturer SPICE models before trusting quantitative results for a specific part.
• Simulation is a check on hand analysis, not a replacement for it. The RC example above is only trustworthy because the hand-calculated τ and final value matched the plotted trace — always compute an expected order of magnitude before running the simulation, so a wrong netlist or unit typo is caught immediately rather than propagating into a design decision.

Key Takeaways

• LTspice workflow: draw schematic → attach a .op/.dc/.ac/.tran directive → run → verify traces in the waveform viewer.
• Every schematic needs a ground reference (node 0); unconnected wire crossings (no dot) are a leading cause of "it doesn't simulate right."
• Component value suffixes matter: meg for mega, m for milli — 1M is parsed as milli, not mega, and silently produces wrong results.
• .ac linearizes around the DC operating point automatically; .tran requires attention to initial conditions for capacitors/inductors.
• Always hand-calculate an expected result (like τ = RC for an RC step response) before simulating, so the simulation output can be verified rather than blindly trusted.