SPICE Simulation: DC, AC, Transient Analysis

SPICE (Simulation Program with Integrated Circuit Emphasis) is the standard way to verify a circuit before it exists in copper. Every op-amp stability check, filter response, power converter loop, or digital I/O rise time you'll ever hand-calculate should also be run through SPICE — hand analysis tells you the expected shape of the answer, SPICE tells you whether parasitics, nonlinearities, and real device models change that answer. Understanding the three core analysis types — DC, AC, and Transient — and what each one actually solves is what separates "I ran a simulation" from "I know what the simulation means."

What SPICE Actually Solves

Underneath every analysis type, SPICE builds a system of equations from Kirchhoff's laws (nodal analysis, generally Modified Nodal Analysis to also handle voltage sources and inductors) and solves for the node voltages and branch currents that satisfy KCL/KVL simultaneously with each component's V-I relationship. The three analyses differ in what kind of solution is being sought:

DC Analysis

.OP finds the single steady-state operating point: all capacitors treated as open circuits, all inductors as short circuits, sources at their DC values. This is the bias point every other analysis builds on — SPICE always computes an operating point first (to linearize transistors and set up initial conditions) before running AC or transient sweeps.

.DC sweeps one or two sources (or a temperature, or a model parameter) and re-solves the operating point at each step — this is how you generate a transistor's I-V curve family, a diode's forward characteristic, or an op-amp's output swing vs. supply.

Why Newton-Raphson matters: diodes, BJTs, and MOSFETs are nonlinear. SPICE linearizes each device around a guess, solves the linear system, updates the guess, and iterates until currents/voltages converge within tolerance (default ~1 µV, 1 pA, or a relative 0.1%, depending on the SPICE variant). Convergence failures ("no convergence in DC analysis") are usually caused by floating nodes, missing DC paths for capacitor-only nodes, or extremely stiff nonlinearities (e.g., an ideal diode with no series resistance) — not a bug in your topology, but a numerical issue you fix with .OPTIONS tweaks or a small ballast resistor.

AC Analysis

.AC performs small-signal analysis: SPICE finds the DC operating point, linearizes every nonlinear device into its small-signal model (transconductance gm, junction capacitances, etc.) around that point, then solves the resulting linear circuit at each frequency using phasors — exactly the impedance/phasor math you'd do by hand, but automated across a frequency sweep (.AC DEC 20 1 1MEG = 20 points/decade from 1 Hz to 1 MHz).

This is how Bode plots (magnitude in dB, phase in degrees) are generated for filters, amplifier loop gain, and power supply compensation. Critically, AC analysis is linear only — it cannot show clipping, slew-rate limiting, or any large-signal distortion. A perfectly stable-looking AC loop gain plot says nothing about whether the circuit clips under a real transient input.

Transient Analysis

.TRAN is the general-purpose, nonlinear, time-domain solver: it steps through time, and at each timestep re-solves the full nonlinear circuit equations (like a sequence of DC operating points, one per instant) while also accounting for the energy storage in capacitors and inductors via numerical integration (trapezoidal or Gear/backward-Euler methods).

• Timestep control: SPICE adapts the step size — smaller during fast transitions (edges, ringing), larger during quiet intervals — bounded by .TRAN parameters (max step) and internal truncation-error estimates.
• Initial conditions: either computed from a DC operating point (default) or forced with .IC / UIC (useful for simulating power-up transients or avoiding a long RC settling time before the interesting event).
• Transient shows everything AC analysis can't: overshoot, ringing, clipping, slew limiting, startup behavior, and switching waveforms.

Worked Example: RC Low-Pass, All Three Analyses

Circuit: 5 V source → 1 kΩ resistor → node out → 100 nF capacitor → ground.

DC: No current flows through the capacitor at steady state (open circuit), so no current flows through R either (single series path with nothing else to ground it through R once C is open) — wait, check the topology: R and C are in series from the source to ground, so at DC the cap is open, meaning zero current flows in the loop, and V(out) = 5 V (no drop across R with zero current). Confirm: I = 0 → V_R = I·R = 0 → V(out) = 5 V − 0 = 5 V. ✓ Consistent with a capacitor holding the full source voltage at DC equilibrium.

AC: Transfer function H(jω) = 1 / (1 + jωRC), pole at f₀ = 1/(2πRC) = 1/(2π·1000·100n) ≈ 1.59 kHz. Running .AC DEC 20 10 1MEG gives a Bode plot flat at 0 dB below 1.59 kHz, rolling off at −20 dB/decade above it, with −3 dB and −45° exactly at 1.59 kHz — matching the hand calculation.

Transient: Step the source from 0 V to 5 V at t = 0 (PULSE(0 5 0 1n 1n 1 1) or simply a V source with .TRAN and UIC for 0 initial capacitor voltage). Time constant τ = RC = 1000·100n = 100 µs. Expect V(out)(t) = 5·(1 − e^(−t/τ)):

• t = τ = 100 µs → V ≈ 5·(1 − 0.368) = 3.16 V
• t = 5τ = 500 µs → V ≈ 5·(1 − 0.0067) = 4.97 V (>99% settled)

Running .TRAN 1u 600u UIC with the capacitor's initial condition set to 0 V should reproduce these values to within simulator numerical tolerance (~mV). If it doesn't match within a few percent, suspect wrong IC, wrong node reference, or a timestep too coarse to resolve the initial fast-charging region — reduce the max timestep and re-check.

Practical Design Implications

• Run all three, not just one. AC tells you bandwidth and stability margin; transient tells you whether the circuit survives a real step, load dump, or startup surge; DC confirms bias points are sane before either matters.
• Match analysis to question. Don't try to infer clipping from an AC plot, and don't try to extract a clean Bode plot from an FFT of a noisy transient run when .AC will give you an exact analytical sweep in seconds.
• Convergence and accuracy are engineering tasks, not simulator magic. Tightening RELTOL, adding sensible series resistances to ideal sources/diodes, and setting realistic initial conditions are routine parts of getting trustworthy results, especially in switching converters and circuits with many nonlinear devices.
• Always sanity-check against hand analysis. A SPICE result that contradicts a first-order RC/RL/Ohm's-law estimate by more than expected parasitic effects is a red flag — check units, node references, and model parameters before trusting the simulator over your own math.

Key Takeaways

• DC (.OP/.DC) solves the nonlinear steady-state operating point via Newton-Raphson iteration; it's the foundation every other analysis linearizes around.
• AC (.AC) linearizes the circuit at its DC bias point and sweeps frequency to produce magnitude/phase (Bode) data — fast and exact, but blind to large-signal/nonlinear effects.
• Transient (.TRAN) solves the full nonlinear time-domain response step by step with numerical integration, capturing everything AC can't: clipping, ringing, switching, startup.
• Always verify simulation results against a hand-calculated first-order estimate (τ = RC, pole frequency, DC bias) — discrepancies beyond expected parasitics usually mean a setup error, not new physics.
• Convergence issues in DC/transient analysis are almost always fixable topology or tolerance problems (floating nodes, missing DC paths, overly ideal models), not simulator failures.