Analog ElectronicsInternubiquitous

Series and Parallel Resistor Combinations

Derive and verify series and parallel resistor equivalents, plus power-dissipation and tolerance pitfalls that matter in real circuit design.

6 min readAhmet Zahid ArıcanUpdated 30 Oct 2026
Dark technical card titled "Series and Parallel Resistor Combinations" showing an RC network schematic above its step response curve in cyan and amber.
Contents & prerequisites

Almost every real circuit, from a simple LED current limiter to a multi-stage filter network, reduces its resistive backbone to combinations of series and parallel resistors. Before a designer can apply Kirchhoff's laws, build a Thevenin equivalent, or size a voltage divider, they need to collapse networks of resistors into a single equivalent value — quickly and correctly. Getting this wrong by even a factor of two changes bias points, cutoff frequencies, and power budgets throughout a design.

Series Combination

Resistors are in series when they carry the same current — they are connected end-to-end with no other current path branching off between them.

  ●───[R1]───[R2]───[R3]───●
  A                        B

Applying KVL around the loop, the total voltage across A–B is the sum of the individual drops:

V_AB = I·R1 + I·R2 + I·R3 = I·(R1 + R2 + R3)

So the equivalent resistance is simply:

R_eq = R1 + R2 + R3 + ... + Rn

Key properties of series resistors:

  • Current is identical through every element (this is the defining condition, not a consequence).
  • Voltage divides in proportion to resistance — the basis of the voltage divider rule (covered in its own article).
  • R_eq is always larger than the largest individual resistor.
  • Adding any resistor in series can only increase total resistance — never decrease it.

Parallel Combination

Resistors are in parallel when they share the same two nodes, so they have the same voltage across them.

  ●───┬───[R1]───┬───●
      │          │
      ├───[R2]───┤
      │          │
      └───[R3]───┘
  A                B

Applying KCL at node A, the total current is the sum of branch currents, each driven by the same voltage V:

I = V/R1 + V/R2 + V/R3

Dividing through by V gives the reciprocal (conductance) form:

1/R_eq = 1/R1 + 1/R2 + 1/R3 + ... + 1/Rn

Key properties of parallel resistors:

  • Voltage is identical across every branch.
  • Current divides inversely with resistance — the current divider rule.
  • R_eq is always smaller than the smallest individual resistor.
  • Adding any resistor in parallel can only decrease total resistance — never increase it.

The Two-Resistor Shortcut

For exactly two resistors in parallel, the reciprocal formula simplifies to the "product over sum" rule, which is worth memorizing because it appears constantly in hand analysis:

R_eq = (R1·R2) / (R1 + R2)

This does not generalize directly to three or more resistors — for three resistors you either sum the reciprocals or apply product-over-sum twice (combine two, then combine the result with the third).

Special Case: N Equal Resistors in Parallel

If N identical resistors of value R are placed in parallel:

R_eq = R / N

This is a fast sanity check: ten 1 kΩ resistors in parallel give 100 Ω; two 100 Ω resistors in parallel give 50 Ω.

Conductance View

Working in conductance G = 1/R (units: siemens) makes parallel combination as simple as series combination in resistance:

Series:    R_eq = ΣR          G_eq = 1 / Σ(1/G)
Parallel:  G_eq = ΣG          R_eq = 1 / Σ(1/R)

Series resistances add directly; parallel conductances add directly. This duality is a recurring theme in circuit theory (it reappears with capacitors, where parallel C adds directly and series C behaves like parallel R).

Worked Example: Mixed Network

Consider the network between node A and ground:

A ──[R1=1kΩ]── N ──┬──[R2=2kΩ]──┐
                    │            ├── GND
                    └──[R3=3kΩ]──┘

R2 and R3 are in parallel between node N and ground; R1 is in series from A to N.

Step 1 — combine the parallel pair:

R23 = (R2·R3)/(R2+R3) = (2000·3000)/(2000+3000) = 6,000,000/5000 = 1200 Ω

Step 2 — add the series element:

R_total = R1 + R23 = 1000 + 1200 = 2200 Ω

Verification by current injection: apply V = 11 V at node A.

  • Total current from source: I = V/R_total = 11/2200 = 5 mA
  • Voltage at node N (drop across R1): V_N = V − I·R1 = 11 − 5m·1000 = 6 V
  • Current through R2: I2 = V_N/R2 = 6/2000 = 3 mA
  • Current through R3: I3 = V_N/R3 = 6/3000 = 2 mA
  • Check KCL at node N: I2 + I3 = 3mA + 2mA = 5 mA = I ✓

The 5 mA supplied at A equals the 5 mA returning through the parallel pair, confirming R_total = 2200 Ω is correct.

Networks That Are Neither Pure Series Nor Pure Parallel

Not every resistor network reduces cleanly by series/parallel inspection. A classic example is the Wheatstone bridge — the standard four-resistor bridge topology, plus any ladder with a resistor bridging two internal nodes — no two resistors share both terminals uniquely, so neither rule applies directly. These require Wye-Delta (Y-Δ) transformation, node/mesh analysis, or Thevenin reduction — each the subject of separate articles in this series. A practical rule of thumb: if you can trace the network and find two elements with a shared, otherwise-unconnected pair of nodes, series/parallel reduction still works piece by piece; if every node has three or more distinct branches with no such isolated pair, you need the more general tools.

Practical Design Implications

  • Standard resistor values: the E12/E24 series don't give arbitrary values. Combining two standard resistors in series or parallel is a common way to hit a precise target (e.g., a 1% divider ratio) without a custom part.
  • Power dissipation splits with the combination type. In series, the resistor with the largest value dissipates the most power (same current, P = I²R). In parallel, the resistor with the smallest value dissipates the most power (same voltage, P = V²/R). Sizing wattage ratings requires checking this, not just the total.
  • Tolerance stacking: in series, absolute tolerances (in ohms) add in the worst case. In parallel, sensitivity is asymmetric: R_eq is only weakly affected by the tolerance of the larger resistor, but becomes increasingly dominated by — and sensitive to — the tolerance of the smallest resistor as the value spread grows. For example, with R1 = 1 kΩ and R2 = 100 Ω, ∂R_eq/∂R2 ≈ 0.83 while ∂R_eq/∂R1 ≈ 0.008, so nearly all of R2's tolerance passes directly into R_eq. Unequal values do not simply "reduce" overall sensitivity — they concentrate it on the smallest resistor.
  • Parasitic resistance matters at extremes. When paralleling many low-value resistors (e.g., current-sense shunts or PCB via arrays), trace and contact resistance in series with each branch can meaningfully skew current sharing — the ideal 1/N result assumes zero parasitic mismatch.
  • Thermal derating in parallel power resistors: paralleling resistors to split power dissipation only works if the resistors have matched values and see matched thermal conditions; otherwise the lower-resistance (or hotter, lower-resistance-drifting) unit hogs current in a positive feedback loop.

Key Takeaways

  • Series: same current through all elements; resistances add directly (R_eq = ΣR); equivalent resistance always exceeds the largest single resistor.
  • Parallel: same voltage across all elements; conductances add directly (1/R_eq = Σ1/R); equivalent resistance is always less than the smallest single resistor.
  • Two-resistor shortcut: R_eq = R1·R2/(R1+R2) for parallel pairs; R_eq = R/N for N equal parallel resistors.
  • Power dissipation is asymmetric: the largest resistor dissipates the most power in series; the smallest dissipates the most in parallel — critical for wattage sizing.
  • Parallel tolerance sensitivity is concentrated, not simply reduced: the smallest-value resistor dominates both R_eq and its tolerance contribution as value spread increases.
  • Not all networks reduce by inspection — bridge-type topologies like the Wheatstone bridge need Y-Δ transformation or nodal/mesh analysis instead.
  • Always verify a reduction with a quick KCL/KVL check on a sample voltage or current, as shown in the worked example — it catches arithmetic slips before they propagate into a design.

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