Thyristor (SCR): Triggering, Latching, Commutation

A thyristor (silicon-controlled rectifier, SCR) is the workhorse switch behind phase-controlled rectifiers, AC motor drives, lamp dimmers, soft-starters and HVDC converter valves. Unlike a BJT or MOSFET, once you turn it on it stays on by itself — the control problem shifts from "how do I sustain conduction" to "how do I turn it off," which is why commutation, not gate drive, dominates SCR circuit design.

Structure and Basic Operation

An SCR is a four-layer p-n-p-n device with three terminals: anode (A), cathode (K), and gate (G). It can be modeled as two complementary BJTs connected regeneratively:

Anode (A)
   |
  [P1]
   |
  [N1] <---- collector of PNP / base of NPN
   |
  [P2] <---- base of PNP / collector of NPN  ---- Gate (G)
   |
  [N2]
   |
Cathode (K)

• Q1 (PNP): emitter at anode, base at N1, collector at P2
• Q2 (NPN): emitter at cathode, base at P2, collector at N1

Q1's collector current feeds Q2's base, and Q2's collector current feeds Q1's base — a positive feedback loop. If the loop gain (α1·α2, the product of the two transistors' common-base current gains) exceeds 1, the pair latches into saturation and the device conducts with a low forward drop (~1–2 V) regardless of what triggered it.

Triggering: How the SCR Turns On

With no gate current, only the leakage current of the reverse-biased middle junction (J2) flows, and α1·α2 ≪ 1 — the device sits in the forward-blocking state even though anode is positive with respect to cathode.

Turn-on requires pushing the loop gain past unity. Four mechanisms do this:

1. Gate triggering (normal use): injecting gate current IG into P2 directly increases Q2's base current, raising Q2's collector current, which raises Q1's base drive, which raises Q1's collector current back into Q2's base — regenerative runaway to full conduction in microseconds. This is the only triggering mode a designer should rely on.
2. Voltage (avalanche) triggering: raising VAK until J2 breaks down by avalanche, generating enough carriers to start the same feedback loop. This is the SCR's forward breakover voltage VBO — treated as an absolute maximum rating, never a design condition.
3. dV/dt triggering: a fast anode voltage step couples displacement current through J2's junction capacitance (i = C·dV/dt), mimicking gate current. Datasheets specify a maximum dV/dt (often 20–1000 V/µs depending on device class); snubbers are added when the application's dv/dt exceeds it.
4. Temperature: leakage current roughly doubles every 10 °C, so α1·α2 drifts toward 1 at high junction temperature, lowering the effective VBO. This is a failure mode to design out, not a trigger method.

Gate trigger requirements: every SCR datasheet specifies minimum IGT and VGT to guarantee turn-on across temperature and manufacturing spread, and maximum ratings (IGM, PGM) to avoid damaging the gate junction. A practical gate drive should deliver several times IGT (fast rise, ~1 µs, amplitude 3–5× IGT is common) to ensure firing under worst-case low-temperature, high-gain-spread conditions, and to minimize turn-on delay time (td) and the associated dI/dt stress during the current rise.

Latching: Why the Gate Loses Control

Once anode current rises above the latching current IL, the regenerative loop is self-sustaining: α1·α2 stays above 1 from the loop's own current, independent of gate current. At this point:

• Removing gate drive does not turn the device off.
• The gate has no further influence on conduction — this is the fundamental difference from a BJT or MOSFET, where the control terminal continuously determines the on/off state.

A closely related but distinct parameter is the holding current IH (IH < IL, typically by ~2–3×): the minimum anode current required to sustain conduction once already latched. If anode current is reduced below IH — by circuit action, not by the gate — the device drops out of conduction and returns to the blocking state. IL matters at turn-on (load current must exceed IL before gate current is removed); IH matters throughout conduction (a lightly loaded or momentarily interrupted circuit can drop below IH and self-commutate unintentionally).

Commutation: How the SCR Turns Off

Because the gate cannot turn an SCR off, the anode current itself must be driven to zero and held there long enough for both junctions to clear their stored charge. This process is commutation, and it's the central design problem in SCR-based power converters.

Natural commutation: in AC circuits (phase-controlled rectifiers, AC line converters), the current naturally crosses zero every half-cycle as the source voltage reverses. No extra circuitry is needed — the SCR turns off automatically at the zero crossing, provided reverse voltage is applied for at least the turn-off time.

Forced commutation: in DC circuits (choppers, inverters built from SCRs rather than fully-controlled devices), the current never naturally reaches zero, so auxiliary components (commutating capacitors/inductors, or an auxiliary SCR) must actively divert or reverse the anode current. This adds size, cost and loss — one major reason IGBTs and MOSFETs displaced SCRs in most DC switching applications, leaving SCRs dominant where line-commutation is free (AC phase control, HVDC).

Turn-off time (tq): after anode current reaches zero, both junctions still hold stored minority charge. Reapplying forward voltage too soon re-triggers the device even with no gate signal — this is the SCR's defining reliability hazard in forced-commutation circuits. tq (typically 10–200 µs, device-dependent) is the minimum interval, measured from the current zero crossing, during which reverse voltage must be sustained before forward voltage is reapplied. Circuit turn-off time in an actual application must exceed the datasheet tq with margin (commonly 2–3×) to allow for temperature and current variation.

Worked Example: Sizing Gate Drive and Checking Commutation Margin

A 50 Hz phase-controlled rectifier uses an SCR with IGT = 30 mA, IL = 150 mA, IH = 40 mA, and tq = 100 µs, switching a resistive load.

Gate drive: choose IG = 150 mA (5× IGT) with a rise time under 1 µs to ensure reliable firing with margin over temperature/spread.

Latching check: the load must pull anode current above IL = 150 mA before the gate pulse ends; with a resistive load and firing near the voltage peak, load current is well above 150 mA within microseconds, so this is satisfied.

Commutation margin: at 50 Hz, each half-cycle is 10 ms. Reverse voltage exists for a portion of the half-cycle after the natural current zero crossing — even a firing angle leaving only 500 µs of reverse-bias window before the next forward half-cycle gives 500 µs / 100 µs = 5× margin over tq. Verification: this is comfortably above the recommended 2–3× minimum, so natural commutation is reliable without a snubber network for turn-off (a snubber may still be needed separately for dV/dt suppression at the next forward blocking transition).

Practical Design Implications

Key Takeaways

• An SCR is a regenerative two-transistor (p-n-p-n) latch: once α1·α2 exceeds 1, it stays on independent of the gate.
• Gate triggering is the only controlled turn-on mechanism; voltage, dV/dt, and thermal triggering are failure modes to avoid by design.
• Latching current IL (needed to sustain conduction as gate drive is removed) and holding current IH (minimum current to stay conducting) are distinct and both matter for reliable operation.
• Turn-off (commutation) requires driving anode current to zero and holding reverse voltage for at least tq — natural commutation is free in AC circuits, forced commutation needs extra components in DC circuits.
• Reapplying forward voltage before tq elapses causes unintended re-triggering with no gate signal present — always design with margin (2–3×) over the datasheet tq.