Triac and Diac: AC Power Control

Classic phase-control lamp dimmers and small universal-motor speed controllers rely on a triac triggered by a diac, while AC solid-state relays use a triac or antiparallel SCRs driven through an optocoupler. Understanding how these devices switch — and why the diac is there at all — is the difference between a dimmer that works over the full rotation of a potentiometer and one that flickers, buzzes, or fails to trigger near the end of its range.

Triac: Structure and Bidirectional Switching

A triac (TRIode for Alternating Current) is functionally two antiparallel SCRs (thyristors) integrated into one five-layer NPNPN structure, sharing a single gate. This lets it conduct current in either direction once triggered, making it suitable for direct AC line switching without a bridge rectifier.

Terminals are labeled MT1 (main terminal 1, the reference for gate voltage), MT2 (main terminal 2), and Gate. Like an SCR, a triac has three operating conditions:

• Blocking (off): high impedance in both polarities, up to its repetitive peak off-state voltage rating V_DRM. Above the breakover voltage it turns on by itself, uncontrolled.
• Latched on: once the gate has started conduction and the main current has risen above the latching current I_L, it stays on with a low on-state drop (typically 1–1.5 V) regardless of further gate signal. The gate only initiates conduction; it doesn't control current magnitude.
• Turn-off (commutation): conduction stops only when the main current falls below the holding current I_H, which happens naturally near each AC zero-crossing.

Because it latches, a triac is a two-state (on/off) switch, not a linear amplifier — all power control comes from when in the AC cycle you trigger it, not from how hard you drive the gate.

The Four Triggering Quadrants

A triac can be triggered with four combinations of MT2-to-MT1 polarity and gate current polarity:

Gate sensitivity in QIV can be several times worse than in the other quadrants, so practical circuits avoid it. A diac-triggered circuit naturally operates in QI and QIII, because the gate pulse always has the same polarity as MT2. MCU- and opto-driven designs often use QII and QIII instead, sending negative gate pulses in both half-cycles. So-called snubberless or 3-quadrant triacs can't be triggered in QIV at all; in exchange, they tolerate much higher commutating dV/dt.

Diac: A Bidirectional Trigger Device

A diac (DIode for Alternating Current) is a two-terminal, three-layer device (an NPN-like but symmetric structure) with no gate. It blocks current in both directions until the voltage across it exceeds its breakover voltage V_BO — typically 28–36 V for common DB3-class parts. At breakover it enters a negative-resistance region: as current rises, the voltage across it folds back by roughly 5–10 V (specified as ΔV, at about 10 mA). That sudden drop dumps the timing capacitor's charge into the triac gate as a sharp current pulse.

Its behavior is symmetric — the same breakover happens in both polarities, and DB3-class parts specify the mismatch between +V_BO and −V_BO (typically within 3 V). That symmetry is exactly what's needed to trigger a triac evenly in both half-cycles of the AC line:

Key point: the diac's snap action means the gate current pulse delivered to the triac rises quickly (a step, not a slow ramp), giving a clean, consistent trigger edge instead of a marginal, jittery turn-on.

Worked Example: RC Phase-Control Dimmer

Classic lamp dimmer topology:

Power path:  L ── MT2 [TRIAC] MT1 ── LOAD ── N
Timing:      MT2 ── R (pot, 1 kΩ–100 kΩ) ── node A ── C (100 nF) ── MT1
Trigger:     node A ── DIAC ── Gate

The timing network sits across the triac, so it sees the line voltage while the triac is off and collapses to about 1 V once it fires.

Assume: 230 V RMS, 50 Hz line (V_pk ≈ 325 V, ω = 2π·50 ≈ 314 rad/s), R adjustable 1 kΩ–100 kΩ, C = 100 nF, diac V_BO = 32 V.

RC time constant: τ = R·C. For R = 50 kΩ (mid-pot):

τ = 50,000 Ω × 100×10⁻⁹ F = 5×10⁻³ s = 5 ms

Compare this with the 10 ms half-cycle at 50 Hz. A 5 ms RC time constant is a significant fraction of the half-cycle, so the capacitor voltage lags the line voltage substantially. That delays the diac breakover point into the half-cycle, cutting the conduction angle and dimming the lamp.

Firing angle: treating the RC network as a linear divider in sinusoidal steady state (see phasor representation and complex impedance), the capacitor voltage lags the line by φ and is reduced in amplitude:

φ      = arctan(ω·R·C)
V_C,pk = V_pk / √(1 + (ω·R·C)²)

The diac fires when the capacitor voltage reaches V_BO, so the firing angle α — measured from the line zero-crossing — is the lag plus the extra angle needed to climb to V_BO:

α ≈ φ + arcsin(V_BO / V_C,pk)

For R = 50 kΩ:

ω·R·C  = 314 × 50,000 × 100×10⁻⁹ ≈ 1.57
φ      = arctan(1.57) ≈ 57.5°
V_C,pk = 325 / √(1 + 1.57²) ≈ 175 V
α      ≈ 57.5° + arcsin(32 / 175) ≈ 57.5° + 10.6° ≈ 68°

For a resistive load, the delivered power relative to full conduction is:

P / P_full = 1 − α/π + sin(2α)/(2π)      (α in radians)

The direction is right — larger R, later firing, dimmer lamp — but the table also exposes the limit of a single RC stage: with C = 100 nF, the 100 kΩ end of the pot only reaches about 91°, roughly half power. Going further needs more resistance, and the response gets steep: at 200 kΩ, α ≈ 120° (≈ 20% power); at 300 kΩ, α ≈ 153° (≈ 2%); above about 320 kΩ the capacitor never reaches V_BO and the lamp goes out abruptly. That steep, unstable end of the range is why practical dimmers add a second RC stage or choose the pot value carefully. The model ignores diac loading and the charge the capacitor loses at each firing, so treat it as a design estimate and confirm on the bench.

Why the Diac Instead of Direct RC-to-Gate Drive

Driving the triac gate directly from the RC network (no diac) is unreliable because:

• Too little gate current. Through tens of kilohms, the RC node can source only a few milliamps — often below the triac's gate trigger current I_GT. Firing then happens late, jitters from cycle to cycle, or doesn't happen at all, which shows up as flicker. With a diac, C charges quietly to V_BO and then dumps its stored charge into the gate as a short pulse of hundreds of milliamps.
• Asymmetric half-cycles. Gate sensitivity differs between QI and QIII (I_GT in QIII is often noticeably higher), so a slow, direct RC drive fires the two half-cycles at different phase angles. The result is asymmetric conduction, a DC component in the load current, and possible saturation of any transformer in the circuit.

The diac's negative-resistance snap decouples the RC timing, which sets when breakover occurs, from the speed and size of the resulting gate pulse, which is fast regardless of how slowly the capacitor charged. The result is consistent, symmetric triggering across both polarities.

Practical Design Considerations

• Snubber network: with inductive loads (motors, transformers), a triac can falsely retrigger from the fast voltage rise right after commutation. An RC snubber across MT1–MT2 (typically 47–100 Ω with 10–100 nF) limits that dV/dt. Don't make the resistor much smaller, or the snubber capacitor discharges into the triac at turn-on with a damaging di/dt. Alternatively, use a snubberless (3-quadrant) triac rated for high commutating dV/dt. Purely resistive lamp loads usually don't need a snubber.
• Control range and hysteresis: single-stage RC dimmers show "snap-on" hysteresis. Turning the pot up from off, the lamp suddenly comes on at a moderate brightness, because once the diac starts firing, the capacitor is partly discharged every half-cycle and the timing shifts. A second RC stage reduces this hysteresis and extends the usable range toward low brightness. A fixed resistor of a few kilohms in series with the pot sets maximum brightness and protects the pot and diac at the low-resistance end.
• RFI/EMI: each firing creates a fast current step that generates conducted and radiated interference. A series choke plus an X2 capacitor across the line is the standard filter for meeting conducted-emission limits (CISPR 15 for lighting equipment). Phase control also draws non-sinusoidal current, so check the product's harmonic-emission limits (IEC 61000-3-2 in Europe).
• Zero-crossing vs phase-control: for resistive heating loads without dimming, zero-crossing switching (firing only near V ≈ 0) minimizes EMI. Triacs used this way are typically driven through an opto-triac zero-cross driver rather than an RC/diac network (see gate drive isolation). Don't zero-cross switch transformers: energizing a transformer at voltage zero produces the worst-case magnetizing inrush.
• Thermal design: conduction loss is roughly 1 W per amp RMS; datasheets give the exact form, P ≈ V_T0·I_T(AV) + r_T·I_T(RMS)². In free air, a TO-220 triac is typically good for only about 1 A RMS; beyond that it needs a heatsink sized to keep the junction temperature within the datasheet limit at the required I_T(RMS).

Key Takeaways

• A triac is a bidirectional thyristor (two antiparallel SCRs in one package) that latches on once gate-triggered with main current above I_L, and turns off naturally near the AC zero-crossing when current drops below I_H.
• QIV is the least sensitive quadrant and is avoided: diac-triggered designs run in QI and QIII, MCU- and opto-driven designs often in QII and QIII.
• A diac is a symmetric, gateless breakover device that snaps into conduction above V_BO (~28–36 V typical), delivering a fast, consistent trigger pulse to the triac gate regardless of how slowly the RC timing network charged.
• In an RC phase-control dimmer, the firing angle is roughly α ≈ arctan(ωRC) + arcsin(V_BO / V_C,pk): increasing R delays firing and dims the load, but a single RC stage gets steep and unstable near the dim end of its range.
• Snubber networks across MT1–MT2, or snubberless triacs, prevent dV/dt-induced false retriggering when driving inductive loads.