Complementary MOS (CMOS): NMOS + PMOS Pairing

CMOS is the reason digital logic dominates modern electronics: a properly designed CMOS gate draws essentially zero static current, so a chip with billions of transistors can sit idle for years on a coin cell. Understanding why the NMOS/PMOS pairing achieves this — and where the "essentially zero" breaks down in practice — is fundamental to reading any digital IC datasheet, power budget, or SPICE deck.

The Basic Pairing

CMOS (Complementary Metal-Oxide-Semiconductor) logic pairs an NMOS and a PMOS transistor so that, for any static input, exactly one of the two is off (in cutoff) and the other is on (in the triode/linear region), never both on and never both off.

        VDD
         |
        PMOS  (source at VDD, gate = Vin)
         |
        ----o Vout
         |
        NMOS  (source at GND, gate = Vin)
         |
        GND

This is the CMOS inverter. Both gates are tied to the same input node, and both drains are tied to the output node.

• Vin = 0 (logic low): NMOS gate-source voltage V_GS = 0 → NMOS off (V_GS < V_TN). PMOS gate-source voltage V_GS = Vin − VDD = −VDD, which is more negative than −|V_TP| → PMOS on, pulling Vout to VDD.
• Vin = VDD (logic high): NMOS V_GS = VDD, well above V_TN → NMOS on, pulling Vout to GND. PMOS V_GS = VDD − VDD = 0 → PMOS off.

In both steady states, the series NMOS–PMOS stack has one device in cutoff, which presents a near-infinite resistance in series with the other's on-resistance. The result: no DC current path from VDD to GND, and the output is actively driven (not left floating) to either rail through a low-impedance on transistor.

Why "Complementary" Matters: Comparing to Single-Polarity Logic

Older NMOS-only logic used a resistor or a always-on NMOS as a pull-up load, which meant one branch was always conducting some current — a static power drain even when idle. CMOS eliminates that:

The key structural trick: the PMOS pull-up and NMOS pull-down are never simultaneously conductive in steady state, because their threshold conditions are complementary — NMOS turns on with a high gate voltage, PMOS turns on with a low gate voltage, and they share the same input.

Device-Level Requirements for the Pairing to Work

For the complementary behavior to hold across the full supply range, both devices' threshold voltages must sit strictly inside the supply rails with margin:

0 < V_TN < VDD
0 < |V_TP| < VDD

If either threshold is too close to 0 or too close to VDD, the "off" device may not be fully off at the nominal input levels, reintroducing a static leakage path. This is a design/process concern in advanced nodes where VDD has shrunk toward 1 V or below while threshold voltages haven't scaled proportionally — a major driver of subthreshold leakage in modern CMOS (see short-channel effects).

Sizing: because electron mobility exceeds hole mobility (typically μₙ/μₚ ≈ 2–3 in bulk silicon), a PMOS with the same channel length needs roughly 2–3× the width of the NMOS to match drive strength (on-resistance / rise and fall times). This is why layout of a "matched" CMOS inverter shows a visibly wider PMOS.

Switching Behavior: Where the Real Power Goes

Static (DC) current is near zero, but CMOS gates are not lossless — power is dissipated in two other mechanisms:

1. Dynamic (switching) power — charging and discharging the load capacitance C_L every transition:

P_dynamic = C_L · VDD² · f

where f is the switching frequency. This dominates total power in most digital CMOS circuits and is why VDD scaling (lower supply voltage) has been the primary lever for reducing chip power across process generations — power falls with the square of VDD.

2. Short-circuit (crossover) current — during the brief transition region where Vin passes through the range where both transistors are partially on (V_TN < Vin < VDD − |V_TP|), a momentary current path exists from VDD to GND even with no external load. This current pulse scales with input slew rate: slower edges keep both devices partially conductive longer, increasing short-circuit energy per transition. Fast, clean edges (steep input transitions) minimize this term.

Worked Example: Static Power Check

Take a CMOS inverter with VDD = 1.8 V, V_TN = 0.4 V, |V_TP| = 0.45 V, and subthreshold leakage current I_leak ≈ 5 nA per transistor (a realistic order of magnitude for a mainstream node at room temperature).

With Vin held at logic low (0 V):

• NMOS is off: V_GS = 0 < V_TN, so ideally I_D = 0; realistically, subthreshold leakage gives I_D ≈ 5 nA.
• PMOS is on: it conducts to pull Vout to VDD, but once Vout settles at VDD, no current flows through the on PMOS either, because the output node isn't sourcing current anywhere (assume no load, or a purely capacitive load already charged).

Static current through the stack is therefore just the off-transistor's leakage, ≈ 5 nA. Static power:

P_static = VDD · I_leak = 1.8 V × 5 nA ≈ 9 nW

Compare to dynamic power at, say, C_L = 50 fF switching at f = 1 GHz:

P_dynamic = C_L · VDD² · f = 50e-15 F × (1.8 V)² × 1e9 Hz
          = 50e-15 × 3.24 × 1e9
          ≈ 1.62e-4 W = 162 µW

Check: 162 µW vs. 9 nW — dynamic power is roughly four orders of magnitude larger in an actively switching gate. This confirms the standard rule of thumb: static leakage is negligible for actively clocked logic but becomes the dominant term for circuits that sit idle for long periods (standby/sleep modes), which is exactly why leakage reduction techniques (power gating, multi-Vt cells, body biasing) matter for battery-powered and always-idle designs.

Practical Design Implications

• Every logic gate is built from this pairing: NAND, NOR, and complex gates are just series/parallel combinations of PMOS pull-up networks and NMOS pull-down networks, always built as logical duals of each other.
• Cross-conduction (short-circuit current) increases with slow input edges — a key reason input buffers and clock trees are designed for fast slew rates.
• Latch-up risk: the parasitic bipolar structures formed by adjacent NMOS/PMOS wells can form a parasitic SCR-like path; proper well/guard-ring layout prevents this from becoming a destructive failure mode.
• Threshold voltage margin shrinks at low VDD, increasing subthreshold leakage — a first-order concern in nanometer-node and low-power design.
• PMOS is sized wider than NMOS (commonly 2–3×) for symmetric rise/fall times, at the cost of larger area and gate capacitance.

Key Takeaways

• CMOS pairs an NMOS and PMOS transistor so that exactly one is on and one is off for any static logic level, eliminating a continuous DC current path.
• The complementary switching requires 0 < V_TN < VDD and 0 < |V_TP| < VDD; violating this margin reintroduces leakage.
• Static power is dominated by subthreshold leakage (nanowatts per gate); dynamic power (P = C_L·VDD²·f) and short-circuit current dominate in actively switching circuits — often by 3–4 orders of magnitude.
• PMOS devices are sized wider than NMOS (roughly 2–3×) to compensate for lower hole mobility and balance rise/fall times.
• Lowering VDD is the most effective lever for reducing dynamic power (quadratic dependence), but it tightens threshold margins and raises leakage — the fundamental power/leakage trade-off in modern CMOS scaling.