Two-Stage Op-Amp: Differential Input + Common-Source Output

The two-stage op-amp — a differential pair driving a common-source gain stage — is the workhorse topology behind the vast majority of general-purpose amplifiers, error amplifiers in LDOs, and integrator stages in sigma-delta modulators. Unlike a single-stage folded-cascode or telescopic amp, it decouples the requirements of high gain and wide output swing into two separate stages, each optimized for its own job. Understanding its gain, pole structure, and compensation is a prerequisite for essentially every other op-amp topology on this roadmap.

Topology Overview

        VDD                                   VDD
         |                                      |
        [M3]---[M4]                          [M6] (PMOS, CS load)
         |       |                              |
   Vin+--[M1] [M2]--Vin-                        |
         |       |                    Vbias1----[M6 gate]
         +---+---+                              |
             |                       Vout <------+------ Cc
            [M5] (tail)                          |
             |                                  [M7] (NMOS, CS driver)
            GND                       node A ----[M7 gate] (from M2 drain)
                                                  |
                                                 GND

Stage 1 — differential pair (M1/M2) with current mirror load (M3/M4): converts the differential input Vin+ − Vin− to a single-ended voltage at node A (drain of M2 / M4), with tail current source M5 setting the bias.

Stage 2 — common-source amplifier (M7) with current-source load (M6): takes node A as its gate input and provides the second stage of voltage gain plus the large output swing that a single differential stage cannot deliver on its own (an unbuffered diff-pair output is limited to roughly one Vov below the top rail).

Miller capacitor Cc: connects node A to Vout, providing frequency compensation (discussed below).

DC Gain

Each stage contributes a gain equal to its transconductance times the resistance at its output node.

Av1 = gm1 · (ro2 ‖ ro4)        (stage 1: diff pair into mirror load)
Av2 = gm7 · (ro6 ‖ ro7)        (stage 2: common-source)

Av,total = Av1 · Av2 = gm1·gm7·(ro2‖ro4)·(ro6‖ro7)

Because gain is the product of two stages rather than one, the two-stage topology reaches DC gains of 60–80 dB with modest cascoding (or even none), where a single-stage telescopic or folded-cascode amp needs cascode devices to hit similar numbers. This is the central appeal: gain without stacking transistors that eat into output swing.

Worked example

Assume 180 nm-class devices at a moderate bias point:

• gm1 = 1 mA/V, ro2 = ro4 = 200 kΩ → Av1 = 1m × (200k‖200k) = 1m × 100k = 100 V/V = 40 dB
• gm7 = 2 mA/V, ro6 = ro7 = 100 kΩ → Av2 = 2m × (100k‖100k) = 2m × 50k = 100 V/V = 40 dB

Av,total = 100 × 100 = 10,000 V/V = 80 dB

Check: 40 dB + 40 dB = 80 dB in log domain — the dB values add correctly because gain in dB is simply 20·log₁₀ of a linear gain, and log(A·B) = log A + log B, so cascaded multiplicative gains always sum in the log domain.

Two Dominant Nodes → Two Poles

The price of two gain stages is two high-impedance nodes, hence two poles in the open-loop transfer function:

p1 ≈ 1 / [2π · Rout1 · Cc·(1+Av2)]     (dominant pole, node A — Miller-multiplied)
p2 ≈ gm7 / (2π · CL)                    (output pole, node Vout)

Without compensation, p1 and p2 sit close together (both are high-impedance internal nodes), giving poor phase margin. This is why virtually every two-stage design uses Miller compensation: Cc bridges node A to Vout, and the Miller effect multiplies its apparent capacitance at node A by (1+Av2), pushing p1 to a much lower frequency while p2 is pushed higher by the same feedback action (pole splitting). The result is a dominant-pole response with p2 placed near or beyond the unity-gain frequency, giving adequate phase margin — this is covered in depth in the dedicated Miller/feedforward/nested-Miller compensation article, but no two-stage design can be discussed without at least this qualitative picture.

A second consequence of Cc: it creates a right-half-plane (RHP) zero, from the feedforward path through Cc that bypasses the gain of stage 2:

z_RHP ≈ gm7 / (2π · Cc)

This zero adds phase lag (opposite sign to a normal LHP zero), which can erode phase margin if not pushed well above the unity-gain frequency. Common fixes: a nulling resistor in series with Cc, or cascode compensation (its own article) to eliminate the feedforward path altogether.

Slew Rate

The tail current sets the maximum rate the first stage can charge/discharge Cc, which dominates the overall slew rate:

SR ≈ I_tail / Cc

This is a hard trade-off: shrinking Cc for higher bandwidth (since GBW = gm1/(2π·Cc)) also improves slew rate, but reducing Cc too far reduces phase margin, since it changes the pole-splitting ratio. Sizing Cc is therefore a joint decision between GBW target, phase margin, and slew rate budget — never in isolation.

Numeric Check: GBW and Compensation Sanity

Take gm1 = 1 mA/V from above, and choose Cc = 2 pF for a target unity-gain bandwidth:

GBW = gm1 / (2π·Cc) = 1×10⁻³ / (2π × 2×10⁻¹²) ≈ 79.6 MHz

Check the RHP zero location with gm7 = 2 mA/V:

z_RHP = gm7 / (2π·Cc) = 2×10⁻³ / (2π × 2×10⁻¹²) ≈ 159.2 MHz

Notice the ratio z_RHP / GBW = gm7/gm1 = 2, regardless of Cc — the zero sits only one octave above the crossover, not a decade. That is uncomfortably close: at 159 MHz the RHP zero already contributes tens of degrees of extra phase lag right at the unity-gain frequency, eating into phase margin. This is why a bare Miller-compensated two-stage amp with gm7 only 2× gm1 typically needs a nulling resistor (or a larger gm7/gm1 ratio, e.g. 5–10×) to push z_RHP out to the recommended 5–10× GBW. If Cc were instead increased to 20 pF, both GBW and z_RHP scale down together (GBW ≈ 8 MHz, z_RHP ≈ 15.9 MHz) — the ratio stays fixed at 2×, confirming that changing Cc alone never fixes the RHP zero problem; only gm7/gm1 (device sizing/bias) or an explicit nulling resistor can.

Design Trade-offs vs. Single-Stage Architectures

Common-Mode and Offset Considerations

The differential input stage inherits all the standard first-stage concerns: gm/tail-current relationship (see the CMOS differential pair article), systematic offset from mirror mismatch, and random offset from device mismatch (see the input offset voltage article). The second CS stage adds negligible input-referred offset since its own offset is divided by the first stage's gain when referred back to the input — a general property of multi-stage amplifiers: offset and noise contributed by later stages shrink by the gain of everything preceding them.

Practical Design Flow

1. Size the diff pair (M1/M2) for required gm1 and input-referred noise/offset target.
2. Size the mirror load (M3/M4) and tail source (M5) for headroom and CMRR.
3. Size the CS output stage (M6/M7) for required output swing and load-driving gm7, keeping gm7/gm1 large enough (typically ≥5×) to help push the RHP zero out.
4. Pick Cc for target GBW = gm1/(2π·Cc), then verify z_RHP = gm7/(2π·Cc) sits ≥5–10× above GBW — remember this ratio equals gm7/gm1 and does not change with Cc, so if it fails, fix gm7/gm1 or add a nulling resistor, not Cc.
5. Simulate open-loop AC response (SPICE .AC) to confirm phase margin ≥ 45–60° at the 0 dB crossover.
6. Check slew rate = I_tail/Cc against the settling-time spec, iterate Cc/I_tail jointly if it fails.

Key Takeaways

• A two-stage op-amp cascades a differential input stage (gain via gm·Rout) with a common-source output stage, multiplying their gains for 60–80+ dB total DC gain without needing cascode stacking.
• The output CS stage buys wide swing that a single differential stage alone cannot deliver.
• Two high-impedance internal nodes create two poles; Miller compensation (Cc from the CS input node to output) splits them into a dominant pole and a pushed-out second pole, at the cost of an RHP zero at gm7/(2π·Cc).
• The RHP zero-to-GBW ratio equals gm7/gm1 and is independent of Cc — sizing Cc bigger or smaller shifts both frequencies together but never fixes a marginal ratio; fix it via device sizing (gm7/gm1) or a nulling resistor.
• Slew rate (I_tail/Cc) and GBW (gm1/(2π·Cc)) are coupled through Cc — sizing it is always a joint decision, verified against the RHP zero location.
• Compared to single-stage folded-cascode/telescopic amps, the two-stage topology trades some bandwidth and power efficiency for higher gain and output swing, making it the default choice for LDO error amplifiers and general-purpose feedback amplifiers.