Parasitic Extraction: StarRC, Quantus RC Extraction

Why parasitic resistance and capacitance matter in sign-off

Parasitic extraction is the process of converting layout geometry — metal shapes, vias, and the dielectric stack around them — into an electrical model of resistance (R) and capacitance (C) that a timing or signal-integrity tool can simulate. Every wire on a chip is not an ideal zero-impedance connection; it is a physical conductor sitting in a dielectric, next to other conductors, and that geometry inevitably behaves like a distributed RC network superimposed on the logical netlist.

How layout geometry creates unwanted RC networks

A metal trace has resistance set by its cross-sectional area and sheet resistivity, and it forms capacitance to every neighboring shape: the substrate below, the ground or power plane, and adjacent wires on the same layer or layers above and below. At modern nodes, wires are tall and narrow rather than wide and flat, so sidewall coupling capacitance to the neighbor on either side can exceed the capacitance to the plane beneath it. A single net might have parasitic coupling to a dozen nearby aggressors, each contributing a small RC element that collectively changes propagation delay, slew, and crosstalk-induced noise. This is the same kind of multi-port electrical behavior described abstractly in Two-Port Network Parameters: Z, Y, H, ABCD — a wire with coupling to several neighbors is really an N-port network, and extraction tools build exactly that kind of admittance representation before boiling it down to SPICE-compatible R and C elements.

Impact on timing closure and signal integrity

Unmodeled or underestimated parasitics show up as timing failures that only appear after routing, or worse, after tapeout. A clock tree that looked balanced at the schematic level can skew by tens of picoseconds once real wire RC is added, and a data path that passed static timing analysis with wireload models can fail by 15–20% of its cycle time once post-route extraction is applied — the exact kind of stage-balance problem discussed in Pipeline Design: Stage Balancing, Retiming, Stall/Flush, except here the imbalance is injected by the physical implementation rather than the microarchitecture. Coupling capacitance also creates crosstalk: a quiet victim net next to a fast-switching aggressor can see enough injected charge to flip a sampled value, or enough delay push-out to break a hold constraint.

Extraction accuracy requirements at advanced nodes

At 28 nm and above, 2D approximations with correction factors were often good enough. Below roughly 16 nm, fin-based transistors, double patterning, and self-aligned vias make the dielectric stack and conductor shapes irregular enough that extraction error of even 5–10% in coupling capacitance can erase a hold or setup margin that was already tight. Foundries supply calibrated technology files specifically because generic parallel-plate formulas no longer track silicon within acceptable bounds.

How StarRC extracts parasitic networks from layout

StarRC (Synopsys) builds its parasitic network by combining geometric field-solver results with pattern-matching against pre-characterized structures, trading some first-principles accuracy for runtime that scales to full-chip extraction.

Geometry-based capacitance calculation methods

StarRC decomposes each net's geometry into elementary patterns — parallel wires, perpendicular crossings, via stacks — and looks up or interpolates capacitance values from a pre-solved table built during technology characterization. For non-standard geometry it falls back to a 2.5D or 3D field solver pass. This hybrid approach is why StarRC can process a full SoC layout in hours rather than days while still capturing sidewall and fringe capacitance effects that a naive area-based formula would miss.

Resistance extraction from interconnect and vias

Resistance is computed from sheet resistance per layer, trace width and length, and via resistance tables supplied in the technology file, with corrections for current crowding at bends and via arrays. Multi-via connections are modeled as parallel resistors with mutual coupling where the vias are close enough for current redistribution to matter.

Distributed RC model generation for netlist coupling

Rather than collapsing a wire to a single lumped R and C, StarRC generates a distributed RC ladder with multiple segments along long nets, which matters because a lumped model underestimates delay and slew degradation on wires that are long relative to their RC time constant. The number of segments is configurable and trades accuracy against netlist size for simulation.

Integration with placement and routing tools

StarRC reads routed-database formats directly from place-and-route tools (DEF/LEF-based flows), so extraction runs on the actual post-route geometry rather than an estimate, and results feed back into the same environment for engineering change order (ECO) timing closure.

How Quantus RC differs in speed and accuracy trade-offs

Quantus RC (Cadence) targets the same sign-off accuracy class as StarRC but structures its solver and data handling differently, which shows up mainly in large hierarchical blocks and designs with heavy reuse.

FastCap acceleration vs. full field solver accuracy

Quantus uses accelerated boundary-element and multipole-style methods descended from the FastCap lineage to approximate field solutions quickly, reserving full field-solver precision for critical nets flagged by the user or by automated criticality analysis. This lets a flow run "golden" accuracy only where timing margin is already thin.

Sparse matrix techniques for large-block extraction

For blocks with millions of nets, Quantus exploits sparsity in the coupling matrix — most nets couple meaningfully to only a handful of physical neighbors — to keep memory and runtime roughly linear in design size rather than quadratic, which is what makes full-chip flat extraction on multi-billion-transistor designs tractable at all.

Floating metal and shield handling

Floating metal fill (dummy fill inserted for chemical-mechanical polishing uniformity) and intentional shield structures both perturb the field around signal nets. Quantus explicitly classifies floating shapes and either grounds them, floats them, or merges their effect into neighboring net capacitance depending on a user-set policy, since treating fill as grounded when it is actually floating can overstate coupling capacitance by a significant margin.

When to use Quantus over traditional StarRC flow

The practical choice is usually dictated by which place-and-route and timing signoff tools the rest of the flow already uses, since both tools produce SPEF and both are foundry-qualified, but mixed-vendor flows (Innovus place-and-route with PrimeTime signoff, for instance) are common enough that extraction tool choice is often independent of the rest of the toolchain.

Extraction file formats and netlist coupling

SPEF (Standard Parasitic Exchange Format) structure

SPEF is the industry-standard text (or compressed) format that carries extracted R, C, and coupling data between extraction and timing/SI tools. A simplified excerpt:

*D_NET net_clk1 0.045
*CONN
*I CLK1 I
*CAP
1 net_clk1:1 0.012
2 net_clk1:2 0.008
*RES
1 net_clk1:1 net_clk1:2 3.4
*END

Here 0.045 pF is total net capacitance, the *CAP section lists per-segment capacitance, and *RES lists resistance between internal nodes — this is the distributed ladder model, not a single lumped value.

Distributed vs. lumped RC representation

Lumped models (single R, single C per net) are faster to simulate and adequate for short local interconnect; distributed models with multiple internal nodes are required for long nets, clock trees, and any path where RC delay is a meaningful fraction of the clock period, matching the segmentation strategy StarRC and Quantus both generate internally.

Coupling capacitance annotation between nets

SPEF's *CAP section also lists coupling pairs (net_a net_b value) separately from ground capacitance, which lets static timing analysis apply Miller-factor derating based on switching correlation between aggressor and victim rather than treating all capacitance as fixed.

Integration with timing, power, and signal integrity tools

PrimeTime, Tempus, and SI-aware tools consume SPEF directly to compute delay, slew, dynamic power (from switched capacitance), and crosstalk noise, making SPEF the single handoff artifact between physical extraction and essentially every downstream signoff check.

Setup and rule-based extraction configuration

Technology file (.tf) and extraction rules

The technology file encodes layer stack thickness, dielectric constants, sheet resistance, and via resistance per process layer, supplied and calibrated by the foundry; extraction accuracy is bounded by how well this file matches actual process corners, which is why foundries issue updated technology files with each process design kit revision.

Cross-coupling capacitance threshold settings

Extraction runs expose a coupling threshold (often expressed as a percentage of total net capacitance) below which coupling to a given neighbor is lumped into ground capacitance instead of modeled explicitly, trading SPEF size and runtime against SI accuracy — tightening this threshold is a common first step when crosstalk-related failures appear late in signoff.

Ground plane and shielding considerations

Power and ground meshes act as reference planes that reduce coupling to signal nets; extraction setup must correctly identify which shapes are tied to a stable rail versus floating, since the underlying physics mirrors how a conductive plane terminates field lines in any layered dielectric structure, the same electrostatic behavior described at the material level in Crystal Structure: Silicon Lattice and Covalent Bonds when discussing how charge distributes in a crystalline lattice under field.

Layer-specific resistance and dielectric models

Each metal and via layer gets its own resistivity, thickness, and inter-layer dielectric constant entry; advanced nodes also require modeling low-k dielectric variation and metal line-edge roughness effects, which foundries typically supply as corner-specific (RC-min, RC-typical, RC-max) technology file variants rather than a single nominal value.

Validating extraction results against silicon

Comparing extracted vs. measured parasitics post-silicon

Validation typically uses ring-oscillator test structures or dedicated RC test chips where measured delay or capacitance is compared against extracted predictions; discrepancies beyond a few percent on calibration structures indicate the technology file itself needs correction, not just the extraction setup.

Common extraction errors and debug techniques

Typical errors include missing or misclassified floating fill, incorrect via resistance tables, and coupling thresholds set too loose for noise-sensitive nets; debugging usually starts by re-extracting a small isolated net with a full 3D field solver and comparing against the production flow's result to isolate which approximation is diverging.

Impact of extraction variance on timing margin

Even a well-calibrated flow carries corner-to-corner RC variance from process spread; designs that close timing with near-zero margin at nominal RC are the ones most likely to fail at RC-max or RC-min corners, so signoff methodology mandates checking all extracted corners, not just typical.

Iterative refinement for next-generation nodes

Each new process node requires re-validating extraction methodology against new test silicon before the technology file is trusted for production signoff, since geometric assumptions (line width, aspect ratio, dielectric stack) that held at the previous node often do not transfer directly.

Extraction in the broader sign-off flow

Placement and routing impact on parasitic distribution

Cell placement density and routing congestion directly determine wire length and neighbor proximity, so extraction results are only as good as the router's final geometry — pre-route estimates are useful for early timing but cannot substitute for post-route extraction before signoff.

Feedback loops with CTS and clock distribution

Clock tree synthesis (CTS) tools use early parasitic estimates to balance skew, then re-converge against actual extracted RC after routing, often requiring one or more ECO iterations when extracted skew diverges from the CTS tool's internal model.

Power delivery network extraction requirements

Power grid extraction focuses on resistance (IR drop) and decoupling capacitance rather than signal coupling, and is typically run as a separate extraction pass with coarser granularity than signal-net extraction, since the concern is voltage droop under switching current rather than delay or crosstalk.

Tool interoperability (Cadence, Synopsys, Mentor ecosystems)

SPEF's standardization means StarRC output can feed Cadence Tempus and Quantus output can feed Synopsys PrimeTime, but mixed flows require careful corner and naming-convention alignment since each vendor's defaults for net and pin naming, and for distributed-node granularity, can differ slightly even when both conform to the SPEF specification.