VLSI & Semiconductor
Semiconductor physics, CMOS device/process, digital VLSI, analog IC design, physical design, and EDA tools.
320 topics · 6 with articles
Intern Engineer· 2 of 40
- 2D Materials: Graphene, MoS2, WSe2 for FET ApplicationsArticle coming
- Avalanche Breakdown: Impact Ionization CoefficientRead
- BJT Current Gain β: Emitter Injection Efficiency, Base TransportArticle coming
- BJT High-Frequency: Transit Time, fT, fmaxArticle coming
- Bipolar Junction Transistor (BJT): Minority Carrier ProfileArticle coming
- Carrier Concentration: n and p in Thermal EquilibriumRead
- Carrier Lifetime and Diffusion LengthArticle coming
- Crystal Structure: Diamond Cubic Lattice for Si and GeArticle coming
- Depletion Approximation and Charge NeutralityArticle coming
- Depletion Region: Width, Electric Field, Charge DistributionArticle coming
- Diffusion Current: Fick's Law, Einstein Relation (D = µkT/q)Article coming
- Direct vs. Indirect Bandgap: Optical Emission DifferenceArticle coming
- Donor (n-type) and Acceptor (p-type) Impurity DopingArticle coming
- Drift Current: Mobility, Electric Field, ConductivityArticle coming
- Early Effect: Base-Width Modulation, Output ResistanceArticle coming
- Energy Band Theory: Valence Band, Conduction Band, BandgapArticle coming
- Fermi Level and Fermi-Dirac Distribution FunctionArticle coming
- FinFET Physics: Tri-Gate Channel, VT Control, SCE ReductionArticle coming
- GAA (Gate-All-Around) Nanosheet: Full Gate Wrap-AroundArticle coming
- GaN HEMT: Polarization, 2DEG Density, BreakdownArticle coming
- High-k Dielectric: HfO2, ZrO2 in Metal Gate StackArticle coming
- Intrinsic Carrier Concentration ni: Temperature DependenceArticle coming
- MOSFET Gate Oxide Reliability: TDDB, Fowler-NordheimArticle coming
- MOSFET Hot Carrier Injection (HCI) MechanismArticle coming
- MOSFET Negative Bias Temperature Instability (NBTI)Article coming
- MOSFET Short-Channel Effects: DIBL, CLM, Velocity SaturationArticle coming
- MOSFET Strong Inversion: Linear and Saturation CurrentArticle coming
- MOSFET Subthreshold: Exponential I-V, Subthreshold SwingArticle coming
- MOSFET Threshold Voltage VT: Derivation and Body EffectArticle coming
- Majority and Minority Carriers: np = ni² LawArticle coming
- Minority Carrier Injection and Diffusion in Neutral RegionsArticle coming
- Organic Semiconductor: OFET, OLED Charge TransportArticle coming
- Quantum Confinement: 2D Electron Gas in HEMTArticle coming
- Quantum Tunneling: Direct Tunnel, FN Tunnel in FlashArticle coming
- Recombination Mechanisms: SRH, Radiative, AugerArticle coming
- SiC Power Device: Critical Field, Thermal ConductivityArticle coming
- Strain Engineering: Biaxial and Uniaxial Stress for MobilityArticle coming
- Zener Breakdown: Band-to-Band Tunneling at High FieldArticle coming
- p-n Junction Formation: Built-In Potential VbiArticle coming
- p-n Junction I-V: Shockley Ideal Diode EquationArticle coming
Junior Engineer· 0 of 40
- 3D NAND: Vertical Channel, Staircase Contact, Layer CountArticle coming
- Air-Gap Interconnect: Ultra-Low-k Between Metal LinesArticle coming
- Assist Techniques: WL Boost, NBL, VDD Collapse for SRAMArticle coming
- CMOS Inverter: Power Dissipation (Dynamic, Static, SC)Article coming
- CMOS Inverter: Propagation Delay (tpHL, tpLH) AnalysisArticle coming
- CMOS Inverter: Static Transfer Characteristic, Switching PointArticle coming
- CMOS Latch-Up: Parasitic SCR, Guard Ring PreventionArticle coming
- CMOS NAND Gate: Transistor Sizing, Worst-Case DelayArticle coming
- CMOS NOR Gate: P-Network Stack, Sizing StrategyArticle coming
- CMOS Process Flow: Thermal Oxidation, Ion ImplantationArticle coming
- Chemical Mechanical Planarization (CMP): Global PlanarityArticle coming
- Chemical Vapor Deposition (CVD): LPCVD, PECVD, ALDArticle coming
- Complex CMOS Gate: AOI, OAI Topology, Euler Path LayoutArticle coming
- Damascene Process: Cu Interconnect, Barrier Layer (TaN)Article coming
- Dry Etching: RIE, DRIE, ICP for Silicon and DielectricArticle coming
- Dual Damascene: Via and Trench in Single Lithography StepArticle coming
- Dynamic CMOS Logic: Precharge-Evaluate, Domino LogicArticle coming
- ESD Protection: Diode, GGNMOS, SCR Clamp StructuresArticle coming
- Epitaxial Source-Drain: SiGe for pMOS Compressive StrainArticle coming
- Flash Memory Cell: Floating Gate, Charge Trap (SONOS)Article coming
- HALO Implant: Counter-Doping for Short-Channel VT ControlArticle coming
- Lithography: ArF 193nm, EUV 13.5nm Exposure BasicsArticle coming
- Low-k Dielectric: SiCOH, k < 2.5 for RC Delay ReductionArticle coming
- MRAM (Magnetic RAM): MTJ, STT-MRAM, SOT-MRAMArticle coming
- Metal Gate Electrode: TiN, TaN for High-k Gate StackArticle coming
- PCM (Phase Change Memory): GST Material, Set/ResetArticle coming
- Pass Transistor Logic (PTL): Transmission Gate CMOSArticle coming
- Physical Vapor Deposition (PVD): Sputtering for MetalArticle coming
- Pocket Implant: Reducing DIBL in Short-Channel DevicesArticle coming
- Process Characterization: MOSFET Splits, SRAM Yield TestArticle coming
- RRAM (Resistive RAM): HfOx Switching, Forming ProcessArticle coming
- SRAM Cell: 6T, 8T, 10T Bit Cell and Stability MetricsArticle coming
- SRAM Read/Write Margin: SNM, WNM, RSNM Butterfly CurveArticle coming
- Self-Aligned Contact (SAC): Overlap Tolerance ImprovementArticle coming
- Silicide: CoSi2, NiSi for Contact and Gate ResistanceArticle coming
- Source-Drain Extension: Shallow Junction for Short-ChannelArticle coming
- Stressed Nitride Liner: Tensile (nMOS), Compressive (pMOS)Article coming
- Well and Retrograde Well Implant for Latch-Up SuppressionArticle coming
- eDRAM: 1T1C Embedded DRAM for High-Density CacheArticle coming
- eSiGe (Embedded SiGe): Hole Mobility EnhancementArticle coming
Middle Engineer· 3 of 80
- ANALOG Layout: Common-Centroid, Interdigitated DevicesArticle coming
- AOCV / POCV: Advanced/Parametric OCV Derate TablesArticle coming
- ARM Cortex-M0: Instruction Set, 3-Stage PipelineArticle coming
- Asynchronous Reset vs. Synchronous Reset in FFArticle coming
- BGR Trimming: Curvature Correction, TC TuningArticle coming
- Bandgap Reference (BGR): Brokaw, Widlar TopologiesArticle coming
- Blocking vs. Non-Blocking Assignment: Race ConditionArticle coming
- Branch Predictor: 2-Bit Saturating Counter, BTB, RASArticle coming
- Bus Protocol RTL: AXI4, AHB-Lite, APB Slave InterfaceArticle coming
- CDC Gray-Code FIFO: Pointer Encoding for SafetyArticle coming
- CMOS Differential Pair: gm, ro, CMRR, PSRR AnalysisArticle coming
- Cache Controller RTL: Tag Array, Data Array, Hit/MissArticle coming
- Carry Look-Ahead Adder (CLA) RTL and Gate-LevelArticle coming
- Charge Pump: Dickson, Voltage Doubler, InvertingArticle coming
- Clock Domain Crossing (CDC): Meta-Stability, SynchronizerArticle coming
- Clock Gating: ICG Cell, Active-Low Enable, Latch-FreeArticle coming
- Continuous-Time Delta-Sigma (CT-SDM): Excess Loop DelayArticle coming
- Current Mirror: Simple, Cascode, Wilson, High-SwingArticle coming
- Current-Steering DAC: Unary, Binary, SegmentedArticle coming
- DAC Non-Linearity: INL, DNL, Glitch EnergyArticle coming
- DMA Controller RTL: Descriptor, Burst, Channel PriorityArticle coming
- Datapath Design: Adder, Multiplier, ALU OptimizationArticle coming
- Drive Strength: X1, X2, X4, X8, X16 Cell VariantsRead
- ESD Diode Layout: Anode, Cathode, TIEDOWN ConnectionArticle coming
- Flash ADC: Comparator Array, Encoder, Bubble ErrorArticle coming
- Folded-Cascode Op-Amp: Higher Output SwingArticle coming
- Fully Differential Op-Amp: CMFB Circuit DesignArticle coming
- Guard Ring: Substrate Noise Isolation in Mixed-SignalArticle coming
- Hold Analysis: Hold Slack = tckq + tcomb - thArticle coming
- I2C Controller RTL: Start/Stop, ACK/NACK, ArbitrationArticle coming
- Integer-N and Fractional-N PLL SynthesizerArticle coming
- Interrupt Controller RTL: Priority, Masking, VectoringArticle coming
- Isolation Cell: AND, OR, Latch Clamp at Domain BoundaryArticle coming
- LDO PSR (Power Supply Rejection): Feedforward TechniqueArticle coming
- LDO Regulator: Error Amp, Pass Device, Loop StabilityArticle coming
- Level Shifter: Combinational, Latch-Based Shift CellArticle coming
- Linting Rules: Undriven Nets, Implicit Width, TruncationArticle coming
- MIM Capacitor: Metal-Insulator-Metal for PrecisionArticle coming
- MOM Capacitor: Metal-Oxide-Metal, Fractal CapacitorArticle coming
- Miller Compensation: Dominant Pole, RHP Zero CancellationArticle coming
- Multi-Bit SDM: Internal DAC Mismatch, DEM AlgorithmArticle coming
- Multi-Corner Multi-Mode (MCMM) Timing SignoffArticle coming
- Network-on-Chip (NoC): Mesh, Torus, Router, FlitArticle coming
- On-Chip Variation (OCV): Setup Derate, Hold DerateArticle coming
- Out-of-Order Execution: ROB, Reservation Station, RenameArticle coming
- PLL Architecture: PFD, Charge Pump, Loop Filter, VCOArticle coming
- PLL Loop Filter: Passive (R-C), Active (Op-Amp) DesignArticle coming
- PLL Phase Noise: In-Band (PFD Noise) and Out-of-Band (VCO)Article coming
- Pipeline ADC: Stage Gain Error, Redundancy CorrectionArticle coming
- Pipeline Design: Stage Balancing, Retiming, Stall/FlushRead
- Power Gating: Header (PMOS), Footer (NMOS) CellArticle coming
- R-2R DAC: Ladder Network, MSB/LSB AnalysisArticle coming
- RISC-V: ISA Base RV32I/RV64I, Extension M, A, F, CArticle coming
- RTL Design: Verilog Module, Hierarchy, Naming ConventionArticle coming
- Rail-to-Rail Input: N+P Parallel Differential Pair StageArticle coming
- Rail-to-Rail Output: CS Stage with AB ControlArticle coming
- Recycling Folded-Cascode (RFC): Improved gm EfficiencyArticle coming
- Regulated Cascode (Gain-Boosted) Current MirrorArticle coming
- Retention FF: Balloon Latch for Data Preservation in SleepArticle coming
- SAR ADC: CDAC, Comparator, Digital Logic, SettlingArticle coming
- SC Comparator: Dynamic Latch, Strongarm, Double-TailArticle coming
- SC Integrator: Delaying and Non-Delaying TypeArticle coming
- SDC: create_clock, set_input_delay, set_output_delayArticle coming
- SDC: set_false_path, set_multicycle_path ExceptionsArticle coming
- SPI Controller RTL: CPOL/CPHA, NSS, DMA InterfaceArticle coming
- Shielding: Metal Mesh, Ring, Differential Routing for AnalogArticle coming
- Sigma-Delta ADC: Oversampling, Noise Shaping NTF/STFArticle coming
- Standard Cell Library: INV, BUF, NAND2, NOR2, MUX2, DFFRead
- Superscalar CPU: Issue Width, Execution Units, SchedulerArticle coming
- Switched-Capacitor (SC) Circuits: Charge ConservationArticle coming
- Synchronous Design: Single-Clock, Registered OutputArticle coming
- Synthesis: Boolean Optimization, Technology MappingArticle coming
- Telescopic Cascode Op-Amp: Maximum Speed ArchitectureArticle coming
- Time-Interleaved ADC: Gain, Offset, Timing Mismatch Cal.Article coming
- Timing Analysis: Setup Slack = Tclk - tckq - tcomb - tsuArticle coming
- Two-Stage CMOS Op-Amp: Gain, Phase Margin, GBWArticle coming
- UART Controller RTL: Baud Rate Generator, TX/RX FIFOArticle coming
- UPF (Unified Power Format): Power Domain, Supply SetArticle coming
- VCO: LC Tank, Ring, Relaxation Oscillator ComparisonArticle coming
- Wallace Tree Multiplier: Partial Product ReductionArticle coming
Senior Engineer· 1 of 80
- ATE (Automatic Test Equipment): Advantest, Teradyne SetupArticle coming
- ATPG Pattern Conversion: Stil Format, Compressed PatternsArticle coming
- ATPG: Automatic Test Pattern Generation Algorithms (D, PODEM)Article coming
- Advanced Node Rules: Coloring (SADP), Track Tip-to-TipArticle coming
- Antenna Rule: Antenna Ratio Limit, Diode Fix StrategyArticle coming
- Assertion-Based Verification (SVA): Concurrent PropertiesArticle coming
- At-Speed Test: Transition Fault, Launch-on-CaptureArticle coming
- Automotive Qualification: AEC-Q100 Grade 0/1/2/3Article coming
- Boundary Scan JTAG (IEEE 1149.1): BSR Chain DesignArticle coming
- Bounded Model Checking (BMC): SAT-Based UnrollingArticle coming
- CTS Skew Target: Local Skew < 20 ps in LibraryArticle coming
- CTS Useful Skew: Intentional Skew for Timing SlackArticle coming
- Cell Placement: Legalization, Detailed PlacementArticle coming
- Clock Tree Signoff: Skew, Latency, Jitter BudgetArticle coming
- Clock Tree Synthesis (CTS): H-Tree, Spine, Mesh, HybridArticle coming
- Code Coverage: Statement, Branch, Toggle, FSM CoverageArticle coming
- Congestion-Driven Placement: GCell Overflow MetricArticle coming
- Constrained Random Verification (CRV): Stimulus GenerationArticle coming
- Crosstalk Fix: Net Shielding, Spacing, Buffer InsertionArticle coming
- DFM Rules: Redundant Via, Metal Slotting, CMP DensityArticle coming
- DFT Overview: Testability, Observability, ControllabilityArticle coming
- DRC (Design Rule Check): Calibre DRC Violation CategoriesArticle coming
- DTCO (Design-Technology Co-Optimization): 3nm AwareArticle coming
- Design for Yield (DFY): Critical Area AnalysisArticle coming
- Detailed Routing: Track Assignment, Via OptimizationArticle coming
- ERC (Electrical Rules Check): Floating Gates, Short CircuitsArticle coming
- Electromigration Signoff: Current Density, Average, RMSArticle coming
- Emulation: Cadence Palladium Z1, Synopsys ZeBu ServerArticle coming
- FMEDA: Failure Mode Effect Diagnostic Analysis for SILArticle coming
- FPGA Prototyping: Multi-FPGA Partition, ILA DebugArticle coming
- Fault Models: Stuck-At, Transition, Path Delay, BridgingArticle coming
- Fault Simulation: Parallel, Deductive, Concurrent MethodsArticle coming
- Floorplanning: Die Area, Aspect Ratio, Utilization TargetArticle coming
- Formal CDC Verification: Metastability AnalysisArticle coming
- Formal Equivalence Checking: LEC Conformal, Synopsys FMArticle coming
- Formal Verification: Model Checking, Property CheckingArticle coming
- Functional Coverage: Covergroup, Coverpoint, CrossArticle coming
- Functional Safety DFT: ISO 26262 Diagnostic CoverageArticle coming
- GDS-II / OASIS: Layout Database Format, Layer MappingArticle coming
- Global Routing: GCell Graph, Maze Routing, FLUTEArticle coming
- Hierarchical Design: Hard Macro, Soft Macro, Black BoxArticle coming
- IR Drop Budget: Static and Dynamic Analysis TargetArticle coming
- Inverse Lithography Technology (ILT): Curvilinear MaskArticle coming
- JasperGold: App Suite (CDC, RDC, FPV, UNR)Article coming
- LVS (Layout vs. Schematic): Netlist Comparison, Device CheckArticle coming
- Logic BIST (LBIST): MISR Compactor, PRPG StimulusArticle coming
- Macro Placement: Timing-Driven, Congestion-AwareArticle coming
- Memory BIST (MBIST): March C-, MATS+, Algorithm DesignArticle coming
- Metal Fill: Density Range, Non-Default Fill RulesArticle coming
- Multi-Patterning Coloring: Graph Coloring, Conflict CheckArticle coming
- Open-Source Physical Design: OpenROAD, OpenLane, MagicArticle coming
- Optical Proximity Correction (OPC): Model-Based CorrectionArticle coming
- Parasitic Extraction: StarRC, Quantus RC ExtractionRead
- Post-Layout STA with Parasitics: Setup and Hold SignoffArticle coming
- Post-Silicon Validation: Silicon Bring-Up, JTAG DebugArticle coming
- Power Domain Floorplan: Level Shifter, Isolation Cell RowsArticle coming
- Power During Test: Toggle Rate, Clock Throttling, PartitionArticle coming
- Power Grid Signoff: Voltus, RedHawk IR Drop and EMArticle coming
- Power Planning: Power Rings, Straps, Rails, Via PillarsArticle coming
- Routing Rules: Minimum Width, Spacing, End-of-LineArticle coming
- Safety Mechanism: Lockstep CPU, ECC Memory, CRCArticle coming
- Scan Chain Insertion: MUX-DFF, Clock-Gating BypassArticle coming
- Scan Compression: X-Bounding, XTOL, EDT Scan CompressionArticle coming
- Scan Ordering: Timing-Driven, Power-Aware Scan ChainArticle coming
- Signal Integrity: Crosstalk Noise, Victim-Aggressor ModelArticle coming
- Silicon Correlation: ATE Measurements vs. SimulationArticle coming
- Source Mask Optimization (SMO): Joint Source + Mask Opt.Article coming
- Standard Cell Row: Height, Site, Orientation, Tap CellArticle coming
- Tapeout Checklist: PDK Version, GDS Merge, Seal RingArticle coming
- Test Coverage Target: 99%+ Stuck-At for ProductionArticle coming
- Test Point Insertion: Observation TP, Control TPArticle coming
- Timing-Aware ATPG: Critical Path Delay Fault PatternsArticle coming
- Timing-Driven Placement: Critical Path Net WeightingArticle coming
- UVM Phases: Build, Connect, Start, Run, Wrap-UpArticle coming
- UVM RAL (Register Abstraction Layer): FrontDoor/BackDoorArticle coming
- UVM Testbench: Agent, Sequencer, Driver, Monitor, ScoreboardArticle coming
- VC Formal: Cadence Formal Verification PlatformArticle coming
- Via Enclosure, Extension Rules for Multi-PatterningArticle coming
- iJTAG (IEEE 1687): Embedded Instruments IntegrationArticle coming
- k-Induction and PDR/IC3: Unbounded Proof MethodsArticle coming
Staff Engineer· 0 of 40
- 2.5D Integration: Interposer (Si, Glass, Organic), HBM StackArticle coming
- 3D-IC: Through-Silicon Via (TSV): Diameter, Aspect RatioArticle coming
- 7nm / 5nm / 3nm / 2nm: Key Process Node MilestonesArticle coming
- AlN (Aluminum Nitride): 6.2 eV Bandgap TransistorArticle coming
- Backside Power Delivery Network (BSPDN) at 2nmArticle coming
- CFET (Complementary FET): nMOS + pMOS Stacked VerticalArticle coming
- Carbon Nanotube FET (CNFET): MIT 16nm DemonstrationArticle coming
- Chiplet Architecture: Die Disaggregation BenefitsArticle coming
- CoWoS (Chip-on-Wafer-on-Substrate): TSMC 2.5D ProcessArticle coming
- Cryogenic CMOS: 4K Operation for Quantum ComputingArticle coming
- Diamond FET: Highest Critical Field Power Device ConceptArticle coming
- Die-to-Wafer (D2W) Bonding: Known-Good-Die SelectionArticle coming
- EMIB (Embedded Multi-Die Interconnect Bridge): IntelArticle coming
- EUV Lithography: 13.5 nm, CO2 Laser Plasma SourceArticle coming
- FOPLP (Fan-Out Panel-Level Packaging): Large PanelArticle coming
- Fan-Out WLP (FOWLP): Wafer-Level ReconstitutionArticle coming
- Flip-Chip BGA: Solder Bump, Cu Pillar, UnderfillArticle coming
- Forksheet FET: Isolation Fin Between N and P ForkArticle coming
- Ga2O3 (Gallium Oxide): Ultra-Wide Bandgap Power DeviceArticle coming
- Gate-All-Around (GAA) Nanosheet at 3nm (Samsung / Intel)Article coming
- HBM (High Bandwidth Memory): Stacked DRAM, 1 TbpsArticle coming
- High-NA EUV (0.55 NA): Resolution 8 nm HP LinesArticle coming
- Hybrid Bonding: Cu-Cu Direct Bond, <1 µm PitchArticle coming
- InFO (Integrated Fan-Out): TSMC for Apple A-SeriesArticle coming
- LPDDR5: Low-Power DRAM for Mobile SoC PackageArticle coming
- Multi-Patterning: SADP, SAQP, LELELE for Sub-7nmArticle coming
- Open Compute Project (OCP): Chiplet Summit InterfacesArticle coming
- Package Stress: CTE Mismatch, Warpage, Solder JointArticle coming
- Photonic Integrated Circuit (PIC): Si3N4 Waveguide PlatformArticle coming
- Photonics-Electronics Co-Integration: 3D Monolithic StackArticle coming
- QFN / DFN: Exposed Pad, Thermal Via, PCB DesignArticle coming
- Silicon Photonics: Ring Modulator, Grating CouplerArticle coming
- Superconducting Qubit Interface: Josephson Junction VLSIArticle coming
- System-in-Package (SiP): Multi-Die, Passive, ModuleArticle coming
- TSV Fabrication: Via-First, Via-Middle, Via-Last ProcessArticle coming
- Technology Roadmap: IRDS 2023 Logic and Memory OutlookArticle coming
- Thermal Simulation of Package: JEDEC JESD51 MethodsArticle coming
- UCIe (Universal Chiplet Interconnect Express): StandardArticle coming
- Wafer-to-Wafer (W2W) Bonding: Alignment, Yield ImpactArticle coming
- Wire Bond: Gold, Copper Ball Bond, Wedge BondArticle coming
Distinguished Engineer· 0 of 40
- AI-Driven EDA: Synopsys DSO.ai, Cadence CerebrusArticle coming
- Cadence Innovus / Synopsys Fusion Compiler PnRArticle coming
- Cadence JasperGold: Formal Verification App SuiteArticle coming
- Cadence Palladium Z2: Hardware Emulation PlatformArticle coming
- Cadence Spectre: SPICE-Compatible Analog SimulationArticle coming
- Cadence Virtuoso: Schematic, Layout, Analog SimulationArticle coming
- Cadence vManager: Verification Planning, Coverage MergeArticle coming
- Chip Design Flow: Spec → RTL → Synthesis → PD → TapeoutArticle coming
- Design Reuse: Hard IP, Soft IP, Configurable IP StrategyArticle coming
- Design Review Gates: Schematic, RTL, Synthesis, PD ReviewArticle coming
- EDA Tool Hierarchy: Simulation, Synthesis, PD, SignoffArticle coming
- GF180MCU: GlobalFoundries 180nm Open-Source PDKArticle coming
- IHP SG13G2: Open-Source SiGe 130nm BiCMOS PDKArticle coming
- KLayout: GDS/OASIS Viewer, DRC Script, Open-SourceArticle coming
- MAGIC VLSI: Open-Source Layout Editor for ResearchArticle coming
- MATLAB / Simulink: System-Level DSP and Control DesignArticle coming
- ML for PD: Congestion Prediction, Timing OptimizationArticle coming
- Mentor (Siemens) Calibre: DRC, LVS, PEX, PERCArticle coming
- Mentor DFT Advisor / Synopsys DFT Compiler: Scan InsertArticle coming
- Mentor Questa / ModelSim: Mixed HDL SimulationArticle coming
- Mentor Tessent: Memory BIST, Scan, DiagnosisArticle coming
- Octave: Open-Source MATLAB Alternative for AnalysisArticle coming
- OpenLane: OpenROAD + Yosys + OpenSTA Integrated FlowArticle coming
- OpenROAD: Open-Source RTL-to-GDS Flow (ORFS)Article coming
- OpenSTA: Open-Source Static Timing Analysis ToolArticle coming
- PDK Management: Technology File, DRC Deck, Model CardArticle coming
- PrimeTime (Synopsys) / Tempus (Cadence): STA SignoffArticle coming
- Python (PySpice, ahkab): Open-Source Circuit AnalysisArticle coming
- Sky130 PDK: Google/SkyWater 130nm Open-Source PDKArticle coming
- StarRC (Synopsys) / Quantus (Cadence): Parasitic ExtractionArticle coming
- Synopsys Custom Compiler: Analog/Mixed-Signal DesignArticle coming
- Synopsys Design Compiler / Genus (Cadence) Synthesis FlowArticle coming
- Synopsys HSPICE: Industry-Standard SPICE SimulatorArticle coming
- Synopsys VC Formal: Property Checking, CDC, DPVArticle coming
- Synopsys VCS / Cadence Xcelium: RTL SimulationArticle coming
- Synopsys ZeBu Server 4: FPGA-Based EmulationArticle coming
- Tape-out Sign-off Package: GDS, CDL, LEF, Timing, PowerArticle coming
- Version Control for IC Design: Git + LFS for Large FilesArticle coming
- Voltus (Cadence) / RedHawk (Synopsys): IR Drop SignoffArticle coming
- Yosys: Open-Source Synthesis for FPGA and ASICArticle coming