VLSI & Semiconductor
Semiconductor physics, CMOS device/process, digital VLSI, analog IC design, physical design, and EDA tools.
320 topics · 0 with articles
Intern Engineer· 40
- 2D Materials: Graphene, MoS2, WSe2 for FET Applications
- Avalanche Breakdown: Impact Ionization Coefficient
- BJT Current Gain β: Emitter Injection Efficiency, Base Transport
- BJT High-Frequency: Transit Time, fT, fmax
- Bipolar Junction Transistor (BJT): Minority Carrier Profile
- Carrier Concentration: n and p in Thermal Equilibrium
- Carrier Lifetime and Diffusion Length
- Crystal Structure: Diamond Cubic Lattice for Si and Ge
- Depletion Approximation and Charge Neutrality
- Depletion Region: Width, Electric Field, Charge Distribution
- Diffusion Current: Fick's Law, Einstein Relation (D = µkT/q)
- Direct vs. Indirect Bandgap: Optical Emission Difference
- Donor (n-type) and Acceptor (p-type) Impurity Doping
- Drift Current: Mobility, Electric Field, Conductivity
- Early Effect: Base-Width Modulation, Output Resistance
- Energy Band Theory: Valence Band, Conduction Band, Bandgap
- Fermi Level and Fermi-Dirac Distribution Function
- FinFET Physics: Tri-Gate Channel, VT Control, SCE Reduction
- GAA (Gate-All-Around) Nanosheet: Full Gate Wrap-Around
- GaN HEMT: Polarization, 2DEG Density, Breakdown
- High-k Dielectric: HfO2, ZrO2 in Metal Gate Stack
- Intrinsic Carrier Concentration ni: Temperature Dependence
- MOSFET Gate Oxide Reliability: TDDB, Fowler-Nordheim
- MOSFET Hot Carrier Injection (HCI) Mechanism
- MOSFET Negative Bias Temperature Instability (NBTI)
- MOSFET Short-Channel Effects: DIBL, CLM, Velocity Saturation
- MOSFET Strong Inversion: Linear and Saturation Current
- MOSFET Subthreshold: Exponential I-V, Subthreshold Swing
- MOSFET Threshold Voltage VT: Derivation and Body Effect
- Majority and Minority Carriers: np = ni² Law
- Minority Carrier Injection and Diffusion in Neutral Regions
- Organic Semiconductor: OFET, OLED Charge Transport
- Quantum Confinement: 2D Electron Gas in HEMT
- Quantum Tunneling: Direct Tunnel, FN Tunnel in Flash
- Recombination Mechanisms: SRH, Radiative, Auger
- SiC Power Device: Critical Field, Thermal Conductivity
- Strain Engineering: Biaxial and Uniaxial Stress for Mobility
- Zener Breakdown: Band-to-Band Tunneling at High Field
- p-n Junction Formation: Built-In Potential Vbi
- p-n Junction I-V: Shockley Ideal Diode Equation
Junior Engineer· 40
- 3D NAND: Vertical Channel, Staircase Contact, Layer Count
- Air-Gap Interconnect: Ultra-Low-k Between Metal Lines
- Assist Techniques: WL Boost, NBL, VDD Collapse for SRAM
- CMOS Inverter: Power Dissipation (Dynamic, Static, SC)
- CMOS Inverter: Propagation Delay (tpHL, tpLH) Analysis
- CMOS Inverter: Static Transfer Characteristic, Switching Point
- CMOS Latch-Up: Parasitic SCR, Guard Ring Prevention
- CMOS NAND Gate: Transistor Sizing, Worst-Case Delay
- CMOS NOR Gate: P-Network Stack, Sizing Strategy
- CMOS Process Flow: Thermal Oxidation, Ion Implantation
- Chemical Mechanical Planarization (CMP): Global Planarity
- Chemical Vapor Deposition (CVD): LPCVD, PECVD, ALD
- Complex CMOS Gate: AOI, OAI Topology, Euler Path Layout
- Damascene Process: Cu Interconnect, Barrier Layer (TaN)
- Dry Etching: RIE, DRIE, ICP for Silicon and Dielectric
- Dual Damascene: Via and Trench in Single Lithography Step
- Dynamic CMOS Logic: Precharge-Evaluate, Domino Logic
- ESD Protection: Diode, GGNMOS, SCR Clamp Structures
- Epitaxial Source-Drain: SiGe for pMOS Compressive Strain
- Flash Memory Cell: Floating Gate, Charge Trap (SONOS)
- HALO Implant: Counter-Doping for Short-Channel VT Control
- Lithography: ArF 193nm, EUV 13.5nm Exposure Basics
- Low-k Dielectric: SiCOH, k < 2.5 for RC Delay Reduction
- MRAM (Magnetic RAM): MTJ, STT-MRAM, SOT-MRAM
- Metal Gate Electrode: TiN, TaN for High-k Gate Stack
- PCM (Phase Change Memory): GST Material, Set/Reset
- Pass Transistor Logic (PTL): Transmission Gate CMOS
- Physical Vapor Deposition (PVD): Sputtering for Metal
- Pocket Implant: Reducing DIBL in Short-Channel Devices
- Process Characterization: MOSFET Splits, SRAM Yield Test
- RRAM (Resistive RAM): HfOx Switching, Forming Process
- SRAM Cell: 6T, 8T, 10T Bit Cell and Stability Metrics
- SRAM Read/Write Margin: SNM, WNM, RSNM Butterfly Curve
- Self-Aligned Contact (SAC): Overlap Tolerance Improvement
- Silicide: CoSi2, NiSi for Contact and Gate Resistance
- Source-Drain Extension: Shallow Junction for Short-Channel
- Stressed Nitride Liner: Tensile (nMOS), Compressive (pMOS)
- Well and Retrograde Well Implant for Latch-Up Suppression
- eDRAM: 1T1C Embedded DRAM for High-Density Cache
- eSiGe (Embedded SiGe): Hole Mobility Enhancement
Middle Engineer· 80
- ANALOG Layout: Common-Centroid, Interdigitated Devices
- AOCV / POCV: Advanced/Parametric OCV Derate Tables
- ARM Cortex-M0: Instruction Set, 3-Stage Pipeline
- Asynchronous Reset vs. Synchronous Reset in FF
- BGR Trimming: Curvature Correction, TC Tuning
- Bandgap Reference (BGR): Brokaw, Widlar Topologies
- Blocking vs. Non-Blocking Assignment: Race Condition
- Branch Predictor: 2-Bit Saturating Counter, BTB, RAS
- Bus Protocol RTL: AXI4, AHB-Lite, APB Slave Interface
- CDC Gray-Code FIFO: Pointer Encoding for Safety
- CMOS Differential Pair: gm, ro, CMRR, PSRR Analysis
- Cache Controller RTL: Tag Array, Data Array, Hit/Miss
- Carry Look-Ahead Adder (CLA) RTL and Gate-Level
- Charge Pump: Dickson, Voltage Doubler, Inverting
- Clock Domain Crossing (CDC): Meta-Stability, Synchronizer
- Clock Gating: ICG Cell, Active-Low Enable, Latch-Free
- Continuous-Time Delta-Sigma (CT-SDM): Excess Loop Delay
- Current Mirror: Simple, Cascode, Wilson, High-Swing
- Current-Steering DAC: Unary, Binary, Segmented
- DAC Non-Linearity: INL, DNL, Glitch Energy
- DMA Controller RTL: Descriptor, Burst, Channel Priority
- Datapath Design: Adder, Multiplier, ALU Optimization
- Drive Strength: X1, X2, X4, X8, X16 Cell Variants
- ESD Diode Layout: Anode, Cathode, TIEDOWN Connection
- Flash ADC: Comparator Array, Encoder, Bubble Error
- Folded-Cascode Op-Amp: Higher Output Swing
- Fully Differential Op-Amp: CMFB Circuit Design
- Guard Ring: Substrate Noise Isolation in Mixed-Signal
- Hold Analysis: Hold Slack = tckq + tcomb - th
- I2C Controller RTL: Start/Stop, ACK/NACK, Arbitration
- Integer-N and Fractional-N PLL Synthesizer
- Interrupt Controller RTL: Priority, Masking, Vectoring
- Isolation Cell: AND, OR, Latch Clamp at Domain Boundary
- LDO PSR (Power Supply Rejection): Feedforward Technique
- LDO Regulator: Error Amp, Pass Device, Loop Stability
- Level Shifter: Combinational, Latch-Based Shift Cell
- Linting Rules: Undriven Nets, Implicit Width, Truncation
- MIM Capacitor: Metal-Insulator-Metal for Precision
- MOM Capacitor: Metal-Oxide-Metal, Fractal Capacitor
- Miller Compensation: Dominant Pole, RHP Zero Cancellation
- Multi-Bit SDM: Internal DAC Mismatch, DEM Algorithm
- Multi-Corner Multi-Mode (MCMM) Timing Signoff
- Network-on-Chip (NoC): Mesh, Torus, Router, Flit
- On-Chip Variation (OCV): Setup Derate, Hold Derate
- Out-of-Order Execution: ROB, Reservation Station, Rename
- PLL Architecture: PFD, Charge Pump, Loop Filter, VCO
- PLL Loop Filter: Passive (R-C), Active (Op-Amp) Design
- PLL Phase Noise: In-Band (PFD Noise) and Out-of-Band (VCO)
- Pipeline ADC: Stage Gain Error, Redundancy Correction
- Pipeline Design: Stage Balancing, Retiming, Stall/Flush
- Power Gating: Header (PMOS), Footer (NMOS) Cell
- R-2R DAC: Ladder Network, MSB/LSB Analysis
- RISC-V: ISA Base RV32I/RV64I, Extension M, A, F, C
- RTL Design: Verilog Module, Hierarchy, Naming Convention
- Rail-to-Rail Input: N+P Parallel Differential Pair Stage
- Rail-to-Rail Output: CS Stage with AB Control
- Recycling Folded-Cascode (RFC): Improved gm Efficiency
- Regulated Cascode (Gain-Boosted) Current Mirror
- Retention FF: Balloon Latch for Data Preservation in Sleep
- SAR ADC: CDAC, Comparator, Digital Logic, Settling
- SC Comparator: Dynamic Latch, Strongarm, Double-Tail
- SC Integrator: Delaying and Non-Delaying Type
- SDC: create_clock, set_input_delay, set_output_delay
- SDC: set_false_path, set_multicycle_path Exceptions
- SPI Controller RTL: CPOL/CPHA, NSS, DMA Interface
- Shielding: Metal Mesh, Ring, Differential Routing for Analog
- Sigma-Delta ADC: Oversampling, Noise Shaping NTF/STF
- Standard Cell Library: INV, BUF, NAND2, NOR2, MUX2, DFF
- Superscalar CPU: Issue Width, Execution Units, Scheduler
- Switched-Capacitor (SC) Circuits: Charge Conservation
- Synchronous Design: Single-Clock, Registered Output
- Synthesis: Boolean Optimization, Technology Mapping
- Telescopic Cascode Op-Amp: Maximum Speed Architecture
- Time-Interleaved ADC: Gain, Offset, Timing Mismatch Cal.
- Timing Analysis: Setup Slack = Tclk - tckq - tcomb - tsu
- Two-Stage CMOS Op-Amp: Gain, Phase Margin, GBW
- UART Controller RTL: Baud Rate Generator, TX/RX FIFO
- UPF (Unified Power Format): Power Domain, Supply Set
- VCO: LC Tank, Ring, Relaxation Oscillator Comparison
- Wallace Tree Multiplier: Partial Product Reduction
Senior Engineer· 80
- ATE (Automatic Test Equipment): Advantest, Teradyne Setup
- ATPG Pattern Conversion: Stil Format, Compressed Patterns
- ATPG: Automatic Test Pattern Generation Algorithms (D, PODEM)
- Advanced Node Rules: Coloring (SADP), Track Tip-to-Tip
- Antenna Rule: Antenna Ratio Limit, Diode Fix Strategy
- Assertion-Based Verification (SVA): Concurrent Properties
- At-Speed Test: Transition Fault, Launch-on-Capture
- Automotive Qualification: AEC-Q100 Grade 0/1/2/3
- Boundary Scan JTAG (IEEE 1149.1): BSR Chain Design
- Bounded Model Checking (BMC): SAT-Based Unrolling
- CTS Skew Target: Local Skew < 20 ps in Library
- CTS Useful Skew: Intentional Skew for Timing Slack
- Cell Placement: Legalization, Detailed Placement
- Clock Tree Signoff: Skew, Latency, Jitter Budget
- Clock Tree Synthesis (CTS): H-Tree, Spine, Mesh, Hybrid
- Code Coverage: Statement, Branch, Toggle, FSM Coverage
- Congestion-Driven Placement: GCell Overflow Metric
- Constrained Random Verification (CRV): Stimulus Generation
- Crosstalk Fix: Net Shielding, Spacing, Buffer Insertion
- DFM Rules: Redundant Via, Metal Slotting, CMP Density
- DFT Overview: Testability, Observability, Controllability
- DRC (Design Rule Check): Calibre DRC Violation Categories
- DTCO (Design-Technology Co-Optimization): 3nm Aware
- Design for Yield (DFY): Critical Area Analysis
- Detailed Routing: Track Assignment, Via Optimization
- ERC (Electrical Rules Check): Floating Gates, Short Circuits
- Electromigration Signoff: Current Density, Average, RMS
- Emulation: Cadence Palladium Z1, Synopsys ZeBu Server
- FMEDA: Failure Mode Effect Diagnostic Analysis for SIL
- FPGA Prototyping: Multi-FPGA Partition, ILA Debug
- Fault Models: Stuck-At, Transition, Path Delay, Bridging
- Fault Simulation: Parallel, Deductive, Concurrent Methods
- Floorplanning: Die Area, Aspect Ratio, Utilization Target
- Formal CDC Verification: Metastability Analysis
- Formal Equivalence Checking: LEC Conformal, Synopsys FM
- Formal Verification: Model Checking, Property Checking
- Functional Coverage: Covergroup, Coverpoint, Cross
- Functional Safety DFT: ISO 26262 Diagnostic Coverage
- GDS-II / OASIS: Layout Database Format, Layer Mapping
- Global Routing: GCell Graph, Maze Routing, FLUTE
- Hierarchical Design: Hard Macro, Soft Macro, Black Box
- IR Drop Budget: Static and Dynamic Analysis Target
- Inverse Lithography Technology (ILT): Curvilinear Mask
- JasperGold: App Suite (CDC, RDC, FPV, UNR)
- LVS (Layout vs. Schematic): Netlist Comparison, Device Check
- Logic BIST (LBIST): MISR Compactor, PRPG Stimulus
- Macro Placement: Timing-Driven, Congestion-Aware
- Memory BIST (MBIST): March C-, MATS+, Algorithm Design
- Metal Fill: Density Range, Non-Default Fill Rules
- Multi-Patterning Coloring: Graph Coloring, Conflict Check
- Open-Source Physical Design: OpenROAD, OpenLane, Magic
- Optical Proximity Correction (OPC): Model-Based Correction
- Parasitic Extraction: StarRC, Quantus RC Extraction
- Post-Layout STA with Parasitics: Setup and Hold Signoff
- Post-Silicon Validation: Silicon Bring-Up, JTAG Debug
- Power Domain Floorplan: Level Shifter, Isolation Cell Rows
- Power During Test: Toggle Rate, Clock Throttling, Partition
- Power Grid Signoff: Voltus, RedHawk IR Drop and EM
- Power Planning: Power Rings, Straps, Rails, Via Pillars
- Routing Rules: Minimum Width, Spacing, End-of-Line
- Safety Mechanism: Lockstep CPU, ECC Memory, CRC
- Scan Chain Insertion: MUX-DFF, Clock-Gating Bypass
- Scan Compression: X-Bounding, XTOL, EDT Scan Compression
- Scan Ordering: Timing-Driven, Power-Aware Scan Chain
- Signal Integrity: Crosstalk Noise, Victim-Aggressor Model
- Silicon Correlation: ATE Measurements vs. Simulation
- Source Mask Optimization (SMO): Joint Source + Mask Opt.
- Standard Cell Row: Height, Site, Orientation, Tap Cell
- Tapeout Checklist: PDK Version, GDS Merge, Seal Ring
- Test Coverage Target: 99%+ Stuck-At for Production
- Test Point Insertion: Observation TP, Control TP
- Timing-Aware ATPG: Critical Path Delay Fault Patterns
- Timing-Driven Placement: Critical Path Net Weighting
- UVM Phases: Build, Connect, Start, Run, Wrap-Up
- UVM RAL (Register Abstraction Layer): FrontDoor/BackDoor
- UVM Testbench: Agent, Sequencer, Driver, Monitor, Scoreboard
- VC Formal: Cadence Formal Verification Platform
- Via Enclosure, Extension Rules for Multi-Patterning
- iJTAG (IEEE 1687): Embedded Instruments Integration
- k-Induction and PDR/IC3: Unbounded Proof Methods
Staff Engineer· 40
- 2.5D Integration: Interposer (Si, Glass, Organic), HBM Stack
- 3D-IC: Through-Silicon Via (TSV): Diameter, Aspect Ratio
- 7nm / 5nm / 3nm / 2nm: Key Process Node Milestones
- AlN (Aluminum Nitride): 6.2 eV Bandgap Transistor
- Backside Power Delivery Network (BSPDN) at 2nm
- CFET (Complementary FET): nMOS + pMOS Stacked Vertical
- Carbon Nanotube FET (CNFET): MIT 16nm Demonstration
- Chiplet Architecture: Die Disaggregation Benefits
- CoWoS (Chip-on-Wafer-on-Substrate): TSMC 2.5D Process
- Cryogenic CMOS: 4K Operation for Quantum Computing
- Diamond FET: Highest Critical Field Power Device Concept
- Die-to-Wafer (D2W) Bonding: Known-Good-Die Selection
- EMIB (Embedded Multi-Die Interconnect Bridge): Intel
- EUV Lithography: 13.5 nm, CO2 Laser Plasma Source
- FOPLP (Fan-Out Panel-Level Packaging): Large Panel
- Fan-Out WLP (FOWLP): Wafer-Level Reconstitution
- Flip-Chip BGA: Solder Bump, Cu Pillar, Underfill
- Forksheet FET: Isolation Fin Between N and P Fork
- Ga2O3 (Gallium Oxide): Ultra-Wide Bandgap Power Device
- Gate-All-Around (GAA) Nanosheet at 3nm (Samsung / Intel)
- HBM (High Bandwidth Memory): Stacked DRAM, 1 Tbps
- High-NA EUV (0.55 NA): Resolution 8 nm HP Lines
- Hybrid Bonding: Cu-Cu Direct Bond, <1 µm Pitch
- InFO (Integrated Fan-Out): TSMC for Apple A-Series
- LPDDR5: Low-Power DRAM for Mobile SoC Package
- Multi-Patterning: SADP, SAQP, LELELE for Sub-7nm
- Open Compute Project (OCP): Chiplet Summit Interfaces
- Package Stress: CTE Mismatch, Warpage, Solder Joint
- Photonic Integrated Circuit (PIC): Si3N4 Waveguide Platform
- Photonics-Electronics Co-Integration: 3D Monolithic Stack
- QFN / DFN: Exposed Pad, Thermal Via, PCB Design
- Silicon Photonics: Ring Modulator, Grating Coupler
- Superconducting Qubit Interface: Josephson Junction VLSI
- System-in-Package (SiP): Multi-Die, Passive, Module
- TSV Fabrication: Via-First, Via-Middle, Via-Last Process
- Technology Roadmap: IRDS 2023 Logic and Memory Outlook
- Thermal Simulation of Package: JEDEC JESD51 Methods
- UCIe (Universal Chiplet Interconnect Express): Standard
- Wafer-to-Wafer (W2W) Bonding: Alignment, Yield Impact
- Wire Bond: Gold, Copper Ball Bond, Wedge Bond
Distinguished Engineer· 40
- AI-Driven EDA: Synopsys DSO.ai, Cadence Cerebrus
- Cadence Innovus / Synopsys Fusion Compiler PnR
- Cadence JasperGold: Formal Verification App Suite
- Cadence Palladium Z2: Hardware Emulation Platform
- Cadence Spectre: SPICE-Compatible Analog Simulation
- Cadence Virtuoso: Schematic, Layout, Analog Simulation
- Cadence vManager: Verification Planning, Coverage Merge
- Chip Design Flow: Spec → RTL → Synthesis → PD → Tapeout
- Design Reuse: Hard IP, Soft IP, Configurable IP Strategy
- Design Review Gates: Schematic, RTL, Synthesis, PD Review
- EDA Tool Hierarchy: Simulation, Synthesis, PD, Signoff
- GF180MCU: GlobalFoundries 180nm Open-Source PDK
- IHP SG13G2: Open-Source SiGe 130nm BiCMOS PDK
- KLayout: GDS/OASIS Viewer, DRC Script, Open-Source
- MAGIC VLSI: Open-Source Layout Editor for Research
- MATLAB / Simulink: System-Level DSP and Control Design
- ML for PD: Congestion Prediction, Timing Optimization
- Mentor (Siemens) Calibre: DRC, LVS, PEX, PERC
- Mentor DFT Advisor / Synopsys DFT Compiler: Scan Insert
- Mentor Questa / ModelSim: Mixed HDL Simulation
- Mentor Tessent: Memory BIST, Scan, Diagnosis
- Octave: Open-Source MATLAB Alternative for Analysis
- OpenLane: OpenROAD + Yosys + OpenSTA Integrated Flow
- OpenROAD: Open-Source RTL-to-GDS Flow (ORFS)
- OpenSTA: Open-Source Static Timing Analysis Tool
- PDK Management: Technology File, DRC Deck, Model Card
- PrimeTime (Synopsys) / Tempus (Cadence): STA Signoff
- Python (PySpice, ahkab): Open-Source Circuit Analysis
- Sky130 PDK: Google/SkyWater 130nm Open-Source PDK
- StarRC (Synopsys) / Quantus (Cadence): Parasitic Extraction
- Synopsys Custom Compiler: Analog/Mixed-Signal Design
- Synopsys Design Compiler / Genus (Cadence) Synthesis Flow
- Synopsys HSPICE: Industry-Standard SPICE Simulator
- Synopsys VC Formal: Property Checking, CDC, DPV
- Synopsys VCS / Cadence Xcelium: RTL Simulation
- Synopsys ZeBu Server 4: FPGA-Based Emulation
- Tape-out Sign-off Package: GDS, CDL, LEF, Timing, Power
- Version Control for IC Design: Git + LFS for Large Files
- Voltus (Cadence) / RedHawk (Synopsys): IR Drop Signoff
- Yosys: Open-Source Synthesis for FPGA and ASIC