Hardware HW Engineer
Schematic/component design, PCB layout, signal integrity, analog/digital HW, power/battery, verification, and HW architecture.
280 topics · 0 with articles
Intern Engineer· 40
- 3D Model Assignment for Component
- Alternative Component Cross-Reference
- Approved Vendor List (AVL) Management
- BOM Management: MPN, Manufacturer, Distributor
- Block Diagram to Schematic Translation
- Capacitor: Dielectric (X7R, C0G, Y5V), Voltage
- Component Footprint Creation per IPC-7351
- Component Lifecycle and Obsolescence Mgmt
- Connector: Mechanical and Electrical Spec
- Crystal: Load Cap, ESR, Frequency Stability
- Datasheet Reading: Absolute Maximum Ratings
- Datasheet Reading: Timing Diagrams, Waveforms
- Design Rule Check (DRC) Setup
- Design for Cost: BOM Cost Optimization
- EMI Filter: Ferrite Bead, Pi-Filter Selection
- ESD Protection: TVS, Zener, PESD Component
- Engineering Change Order (ECO) Process
- Fiducial Marker and Board Edge Rules
- IPC-7351 Land Pattern Calculator Usage
- Inductor: DCR, SRF, Saturation Current Selection
- KiCad vs. Altium Designer Comparison
- Mounting Hole and Keepout Zone Setup
- Multi-Channel Schematic Design
- Net Naming Convention and Label Types
- Oscillator vs. Crystal Trade-offs
- Part Library Standardization and Centralization
- Polarized Component Marking (Diode, Cap)
- Power Symbols and PWR_FLAG Usage
- Pre-Layout Signal Integrity Planning
- Reference Designator Numbering Convention
- Resistor: Tolerance, TCR, Power Rating Selection
- Schematic Net Class Definition
- Schematic Page Organization and Hierarchy
- Schematic Review Checklist (ERC)
- Schematic Symbol Creation (IEEE Standard)
- Schematic to Layout Netlist Export
- System-Level Schematic Architecture Review
- Test Point and Debug Header Placement
- Variant Management in Altium Designer
- Version Control with Git for Schematics
Junior Engineer· 40
- 3D PCB in Altium: Enclosure Clearance Check
- AC Coupling Capacitor Placement for High-Speed
- AOI Layer Setup for Factory Inspection
- Assembly Drawing and Fabrication Notes
- BGA Breakout: Dog-Bone, Via-in-Pad Techniques
- Controlled Impedance Trace: Microstrip Formula
- Controlled Impedance Trace: Stripline Formula
- Coplanar Waveguide with Ground (CPWG)
- Copper Balancing and Hatching for CTE
- Crosstalk Reduction: 3W Rule for Traces
- DDR4 / DDR5 Layout: Fly-by Topology
- DDR4 Data Bus Length Matching (+-25 mil)
- Dielectric Material: FR4, Rogers 4350B, Megtron
- Differential Pair Routing: Length Match, Spacing
- Eye Diagram Simulation and Mask Compliance
- Gerber / ODB++ Output and Inspection
- Ground Plane Split Avoidance Under Traces
- High-Power Trace Thermal Management
- Layer Stack-Up for Impedance Control 50/100 Ohm
- Microstrip vs. Stripline Selection Guidelines
- PCB Stack-Up Selection: 2L, 4L, 6L, 8L
- PCIe Gen3 / Gen4 / Gen5 Lane Routing
- Panelization: V-Groove, Tab-Routed
- Post-Layout SI Simulation (HyperLynx)
- Power Integrity: PDN Impedance Simulation
- Power Plane Copper Pour and Thermal Relief
- Pre-Layout SI Simulation with IBIS Models
- SFP+ and QSFP28 High-Speed Interface Layout
- SMA / U.FL RF Connector PCB Integration
- SMD Pad Design per IPC-7351
- Signal Return Path: Ground Plane Continuity
- Silkscreen Placement for Assembly Clarity
- Solder Mask Expansion and LPI Coating
- Stack-Up Symmetry for Warpage Control
- Thermal Relief vs. Solid Via Connection
- Trace Length Matching for Clock Trees
- USB 2.0 / 3.2 / 4.0 Differential Routing Rules
- Via Aspect Ratio and Reliable Plating (IPC-2226)
- Via Stub and Back-Drill for High-Speed Signals
- Via Types: Through-Hole, Blind, Buried, Micro-Via
Middle Engineer· 80
- AC Termination for High-Frequency Signals
- ADC Anti-Aliasing Filter: Butterworth, Sallen-Key
- ADC Input Driver: Settling Time, Bandwidth
- Analog Supply Filtering: LDO + LC Filter
- Automotive MCU Interface: LIN, CAN FD, FlexRay
- Board Factory Test Interface (ICT, Bed-of-Nails)
- Boot Mode Configuration Resistors (Strapping)
- CAN Bus Transceiver, Termination, ESD
- CXL (Compute Express Link) HW Design
- CXL 3.0 High-Bandwidth Memory Interface
- Chip-Select Decoder Logic Design
- Clock Distribution and Jitter Minimization
- Clock Source: HSE Crystal, HSI RC, PLL Config
- Crosstalk Between Analog and Digital Domains
- Current-to-Voltage (TIA) Converter Design
- DAC Output Buffer and Reconstruction Filter
- DDR5 Memory Topology Design
- Delta-Sigma ADC Modulator Input Design
- Difference Amplifier for Noise Rejection
- Display Interface: OLED, TFT, e-Paper Driver
- Ethernet PHY and Magnetic Isolation Circuit
- External Watchdog and Reset Supervisor IC
- FPGA Configuration: JTAG, SPI Flash, USB
- FPGA I/O Standard: LVCMOS, LVDS, SSTL
- FPGA Power Sequencing and Decoupling
- Ground Plane Strategy: Analog/Digital Separation
- HDMI / DVI Interface Circuit and ESD
- Hall Effect Sensor Signal Conditioning
- High-Speed Analog: GHz Op-Amp Selection
- High-Voltage Interface: Optocoupler, Cap Isolation
- Impedance Mismatch and Stub Reflection
- Instrumentation Amplifier for Sensor Signals
- Integrator and Differentiator Op-Amp Circuits
- Interrupt Routing and Priority Assignment
- Isolated RS-485 for Noisy Environments
- Level Shifter: Unidirectional, Bidirectional
- Load Cell and Strain Gauge Amplifier
- Log and Anti-Log Amplifier Design
- Low-Noise Power Rail for Analog Sections
- MCU Selection: Core, Flash, RAM, Peripherals
- MEMS Sensor Interface: Capacitive, Resistive
- MIPI DPHY Termination and PCB Design
- MIPI DSI / CSI-2 Receiver Interface Design
- Memory Interface: External SRAM, HyperRAM
- Mixed-Signal IC Evaluation Board Design
- Multi-MCU Communication: CAN, SPI, I2C
- NAND Flash Parallel Interface Layout
- Noise Budget Allocation in Analog Signal Chain
- Op-Amp GBW, Slew Rate, CMRR, PSRR Specs
- Op-Amp Inverting and Non-Inverting Configuration
- Open-Collector / Open-Drain Pull-Up Design
- Optical Sensor Circuit: Photodiode, Phototransistor
- PCB-Level EMI in Analog Sensor Chains
- PCIe Root Complex to Endpoint Board Design
- Peak Detector and Sample-and-Hold Circuit
- Precision Current Source: PTAT, Adjustable
- Precision Rectifier: Half-Wave, Full-Wave
- Pressure Sensor Wheatstone Bridge Amplifier
- Programmable Gain Amplifier (PGA) Design
- RF-Capable PCB for Analog Chain
- RISC-V SoC Hardware Bring-Up Methodology
- RS-232 Level Shifter Circuit Design
- RS-485 Transceiver and Fail-Safe Resistors
- Rail-to-Rail Op-Amp Selection for Low-Voltage
- Real-Time Clock (RTC) Circuit with Crystal
- Reset Circuit: External Supervisor, Brown-Out
- SAR ADC Reference Voltage Decoupling
- SDRAM / DDR Interface Routing and Termination
- Schmitt Trigger and Hysteresis Design
- Series Termination and Parallel Termination
- Shield Trace and Guard Ring for Analog
- Single-Ended to Differential Conversion
- SoC Platform: NXP, STM32, Nordic, ESP32
- Switched-Mode Noise on Analog Supply Mitigation
- Thermocouple and RTD Signal Conditioning
- USB ESD Protection: D+ and D- Lines
- USB Type-C with CC Logic and PD Controller
- Voltage Comparator: Open Drain vs. Push-Pull
- Voltage-to-Current (Howland) Converter
- Window Comparator Design and Application
Senior Engineer· 40
- 48V Mild Hybrid Automotive Power Design
- Battery Charger IC: CC/CV Charging Algorithm
- Battery Cycle Life vs. Charge Rate Trade-off
- Buck Converter Layout for Minimal EMI
- Bypass Capacitor: ESR, ESL vs. Frequency
- Cell Balancing: Passive vs. Active Topology
- Copper Fill and Thermal Via for Power Dissipation
- Current Probe and Rogowski Coil Measurement
- EMI Filter Optimization with Pre-Compliance
- EMI from Switching Regulator: Radiated, Conducted
- EV Battery Pack: Module, BMS, Contactor
- Energy Harvesting HW: Solar, TEG, Piezo
- Fast Charging: USB PD 3.1, Qualcomm QC 5.0
- Fuel Gauge IC: Coulomb Counter vs. Voltage-Based
- GaN Fast Charger Module (65W, 140W) Design
- High-Voltage Safety Isolation for BMS (>60V)
- Hot-Swap Controller for Live Insertion
- Input EMI Filter: Common-Mode Choke
- LDO Bypass Capacitor CIN / COUT Requirements
- LDO Voltage Regulator Selection and Stability
- Li-Ion Battery Protection IC (OVP, UVP, OCP)
- Multi-Cell BMS Architecture: 2S, 4S, 10S
- OR-ing Circuit for Redundant Power Supplies
- PCB Power Rail Decoupling: Bulk, Mid-Freq, HF
- PDN Impedance Target from IC Datasheet
- PMIC Integration: Multi-Rail Power Management
- Power Architecture Review and System Budget
- Power Efficiency Measurement (E-Load + PA)
- Power Path Management for Battery-Powered
- Power Sequencing Circuit: Supervisor, MOSFET
- Power-Good Signal Usage and Monitoring
- Reverse Polarity Protection: P-MOSFET
- Sequencing Requirements for SoC/FPGA Rails
- Soft-Start Circuit to Limit Inrush Current
- Switching Regulator Component Selection
- TVS and MOV for Surge Protection
- Thermal Management for Charging IC
- USB PD Negotiation: CC Pin, VBUS Profiles
- USB Power Delivery (PD) Sink Controller
- Wireless Charging (Qi 1.3 / Qi 2.0) Coil and IC
Staff Engineer· 40
- AOI (Automated Optical Inspection) Setup
- Active Differential Probe Usage
- BERT (Bit Error Rate Tester) for SerDes
- Boundary Scan Test (JTAG) for PCB Debug
- Burn-In Test Rack Design and Operation
- CAPA (Corrective and Preventive Action)
- Current Probe: Clamp, Rogowski, Coaxial Shunt
- De-Embedding Fixture Effects from VNA
- EFT/Burst Generator: IEC 61000-4-4 Usage
- ESD Simulator: IEC 61000-4-2 Test Setup
- Environmental Screening: Temp Cycling, Humidity
- Eye Diagram Mask Test on Oscilloscope
- FMEA (Failure Modes and Effects Analysis)
- Failure Analysis: SEM, FIB, TEM Techniques
- Flying Probe Test Setup and Coverage
- Functional Test Fixture Design
- HW Failure Investigation and Root Cause Analysis
- ICT (In-Circuit Test) Fixture Design
- In-Circuit Debugger: JTAG, SWD, cJTAG
- Incoming Quality Control (IQC) for Components
- J-Link and OpenOCD Usage for FW Debug
- LCR Meter for Impedance Measurement
- LISN (Line Impedance Stabilization Network)
- Logic Analyzer: State and Timing Mode
- Near-Field EMI Probe Set (H-field, E-field)
- Oscilloscope Probe: 1x vs. 10x vs. 100x
- Oscilloscope: Bandwidth, Sample Rate, Memory Depth
- Power Integrity: PDN Analyzer (Picotest)
- Protocol Decoder: UART, SPI, I2C, CAN, USB
- Qualification: Vibration, Shock, Altitude Tests
- Reliability Testing: HALT, HASS, HAST, THB
- Saleae Logic Pro: Analog + Digital Combined
- Spectrum Analyzer: RBW, VBW, Span Setting
- Surge Generator: IEC 61000-4-5 Test Setup
- TDR for Impedance Profile Measurement
- Thermal Camera: Hot-Spot Identification
- Thermal Chamber: -40C to +85C Profiling
- VNA TRL / SOLT Calibration Procedure
- Vector Network Analyzer (VNA) Basics: S11, S21
- X-Ray Inspection for BGA Solder Joints
Distinguished Engineer· 40
- Backplane Connector and High-Density Interface
- Board-to-Board Connector Stack Height
- Cable Harness Routing and Shielding
- Carrier Board Design for SoM (Jetson, CM4)
- Chiplet-Based System HW Design
- Design Input / Design Output Traceability
- Design for Manufacturing (DFM) Review
- Design for Reliability (DFR): HALT Strategy
- Design for Test (DFT) Planning at System Level
- Digital Twin for HW System Validation
- EMC Architecture: Filtering, Shielding, Grounding
- FPGA + CPU Heterogeneous Platform Design
- Fan and Blower Selection: Airflow Calculation
- Functional Safety Architecture: ISO 26262
- HW Architecture for Space (Rad-Hard, EEE)
- HW Security Architecture: TPM, Secure Element
- HW-SW Co-Design: Timing Closure for HW
- Hardware Architecture Review Process (HAR)
- Heat Pipe and Vapor Chamber in System
- Hot-Swap and Live-Insert Board Architecture
- Interface Control Document (ICD) for Boards
- Multi-Board System Interconnect Design
- Multi-Generation Platform Architecture Planning
- Open Hardware Standards: OCP, ODSA, OIF
- PCIe Backplane Design for Multi-Board
- Platform Reuse and Scalability Strategy
- Prototype Build: EVT, DVT, PVT Milestones
- Redundancy Architecture: N+1, 2N Power Supply
- Requirements Capture: MRD > HRD > Schematic
- SoM vs. Custom PCB Trade-off Analysis
- Supplier Selection: EMS, CM, ODM Comparison
- Sustainability: Low-Power Architecture, RoHS
- System Block Diagram: Top-Down Design
- System Enclosure: Al vs. Steel Shielding
- System Grounding: Single-Point vs. Multi-Point
- System Power Budget: Steady-State and Peak
- Technology Roadmap for HW Platform
- Thermal Budget: Junction Temperature Target
- Thermal Enclosure: Conduction vs. Convection
- Water Cooling Block for High-Power HW