Hardware HW Engineer
Schematic/component design, PCB layout, signal integrity, analog/digital HW, power/battery, verification, and HW architecture.
280 topics · 4 with articles
Intern Engineer· 2 of 40
- 3D Model Assignment for ComponentRead
- Alternative Component Cross-ReferenceRead
- Approved Vendor List (AVL) ManagementArticle coming
- BOM Management: MPN, Manufacturer, DistributorArticle coming
- Block Diagram to Schematic TranslationArticle coming
- Capacitor: Dielectric (X7R, C0G, Y5V), VoltageArticle coming
- Component Footprint Creation per IPC-7351Article coming
- Component Lifecycle and Obsolescence MgmtArticle coming
- Connector: Mechanical and Electrical SpecArticle coming
- Crystal: Load Cap, ESR, Frequency StabilityArticle coming
- Datasheet Reading: Absolute Maximum RatingsArticle coming
- Datasheet Reading: Timing Diagrams, WaveformsArticle coming
- Design Rule Check (DRC) SetupArticle coming
- Design for Cost: BOM Cost OptimizationArticle coming
- EMI Filter: Ferrite Bead, Pi-Filter SelectionArticle coming
- ESD Protection: TVS, Zener, PESD ComponentArticle coming
- Engineering Change Order (ECO) ProcessArticle coming
- Fiducial Marker and Board Edge RulesArticle coming
- IPC-7351 Land Pattern Calculator UsageArticle coming
- Inductor: DCR, SRF, Saturation Current SelectionArticle coming
- KiCad vs. Altium Designer ComparisonArticle coming
- Mounting Hole and Keepout Zone SetupArticle coming
- Multi-Channel Schematic DesignArticle coming
- Net Naming Convention and Label TypesArticle coming
- Oscillator vs. Crystal Trade-offsArticle coming
- Part Library Standardization and CentralizationArticle coming
- Polarized Component Marking (Diode, Cap)Article coming
- Power Symbols and PWR_FLAG UsageArticle coming
- Pre-Layout Signal Integrity PlanningArticle coming
- Reference Designator Numbering ConventionArticle coming
- Resistor: Tolerance, TCR, Power Rating SelectionArticle coming
- Schematic Net Class DefinitionArticle coming
- Schematic Page Organization and HierarchyArticle coming
- Schematic Review Checklist (ERC)Article coming
- Schematic Symbol Creation (IEEE Standard)Article coming
- Schematic to Layout Netlist ExportArticle coming
- System-Level Schematic Architecture ReviewArticle coming
- Test Point and Debug Header PlacementArticle coming
- Variant Management in Altium DesignerArticle coming
- Version Control with Git for SchematicsArticle coming
Junior Engineer· 2 of 40
- 3D PCB in Altium: Enclosure Clearance CheckArticle coming
- AC Coupling Capacitor Placement for High-SpeedArticle coming
- AOI Layer Setup for Factory InspectionArticle coming
- Assembly Drawing and Fabrication NotesArticle coming
- BGA Breakout: Dog-Bone, Via-in-Pad TechniquesRead
- Controlled Impedance Trace: Microstrip FormulaArticle coming
- Controlled Impedance Trace: Stripline FormulaArticle coming
- Coplanar Waveguide with Ground (CPWG)Article coming
- Copper Balancing and Hatching for CTEArticle coming
- Crosstalk Reduction: 3W Rule for TracesArticle coming
- DDR4 / DDR5 Layout: Fly-by TopologyArticle coming
- DDR4 Data Bus Length Matching (+-25 mil)Article coming
- Dielectric Material: FR4, Rogers 4350B, MegtronArticle coming
- Differential Pair Routing: Length Match, SpacingArticle coming
- Eye Diagram Simulation and Mask ComplianceArticle coming
- Gerber / ODB++ Output and InspectionArticle coming
- Ground Plane Split Avoidance Under TracesArticle coming
- High-Power Trace Thermal ManagementArticle coming
- Layer Stack-Up for Impedance Control 50/100 OhmArticle coming
- Microstrip vs. Stripline Selection GuidelinesArticle coming
- PCB Stack-Up Selection: 2L, 4L, 6L, 8LArticle coming
- PCIe Gen3 / Gen4 / Gen5 Lane RoutingArticle coming
- Panelization: V-Groove, Tab-RoutedArticle coming
- Post-Layout SI Simulation (HyperLynx)Article coming
- Power Integrity: PDN Impedance SimulationArticle coming
- Power Plane Copper Pour and Thermal ReliefArticle coming
- Pre-Layout SI Simulation with IBIS ModelsArticle coming
- SFP+ and QSFP28 High-Speed Interface LayoutArticle coming
- SMA / U.FL RF Connector PCB IntegrationArticle coming
- SMD Pad Design per IPC-7351Article coming
- Signal Return Path: Ground Plane ContinuityRead
- Silkscreen Placement for Assembly ClarityArticle coming
- Solder Mask Expansion and LPI CoatingArticle coming
- Stack-Up Symmetry for Warpage ControlArticle coming
- Thermal Relief vs. Solid Via ConnectionArticle coming
- Trace Length Matching for Clock TreesArticle coming
- USB 2.0 / 3.2 / 4.0 Differential Routing RulesArticle coming
- Via Aspect Ratio and Reliable Plating (IPC-2226)Article coming
- Via Stub and Back-Drill for High-Speed SignalsArticle coming
- Via Types: Through-Hole, Blind, Buried, Micro-ViaArticle coming
Middle Engineer· 0 of 80
- AC Termination for High-Frequency SignalsArticle coming
- ADC Anti-Aliasing Filter: Butterworth, Sallen-KeyArticle coming
- ADC Input Driver: Settling Time, BandwidthArticle coming
- Analog Supply Filtering: LDO + LC FilterArticle coming
- Automotive MCU Interface: LIN, CAN FD, FlexRayArticle coming
- Board Factory Test Interface (ICT, Bed-of-Nails)Article coming
- Boot Mode Configuration Resistors (Strapping)Article coming
- CAN Bus Transceiver, Termination, ESDArticle coming
- CXL (Compute Express Link) HW DesignArticle coming
- CXL 3.0 High-Bandwidth Memory InterfaceArticle coming
- Chip-Select Decoder Logic DesignArticle coming
- Clock Distribution and Jitter MinimizationArticle coming
- Clock Source: HSE Crystal, HSI RC, PLL ConfigArticle coming
- Crosstalk Between Analog and Digital DomainsArticle coming
- Current-to-Voltage (TIA) Converter DesignArticle coming
- DAC Output Buffer and Reconstruction FilterArticle coming
- DDR5 Memory Topology DesignArticle coming
- Delta-Sigma ADC Modulator Input DesignArticle coming
- Difference Amplifier for Noise RejectionArticle coming
- Display Interface: OLED, TFT, e-Paper DriverArticle coming
- Ethernet PHY and Magnetic Isolation CircuitArticle coming
- External Watchdog and Reset Supervisor ICArticle coming
- FPGA Configuration: JTAG, SPI Flash, USBArticle coming
- FPGA I/O Standard: LVCMOS, LVDS, SSTLArticle coming
- FPGA Power Sequencing and DecouplingArticle coming
- Ground Plane Strategy: Analog/Digital SeparationArticle coming
- HDMI / DVI Interface Circuit and ESDArticle coming
- Hall Effect Sensor Signal ConditioningArticle coming
- High-Speed Analog: GHz Op-Amp SelectionArticle coming
- High-Voltage Interface: Optocoupler, Cap IsolationArticle coming
- Impedance Mismatch and Stub ReflectionArticle coming
- Instrumentation Amplifier for Sensor SignalsArticle coming
- Integrator and Differentiator Op-Amp CircuitsArticle coming
- Interrupt Routing and Priority AssignmentArticle coming
- Isolated RS-485 for Noisy EnvironmentsArticle coming
- Level Shifter: Unidirectional, BidirectionalArticle coming
- Load Cell and Strain Gauge AmplifierArticle coming
- Log and Anti-Log Amplifier DesignArticle coming
- Low-Noise Power Rail for Analog SectionsArticle coming
- MCU Selection: Core, Flash, RAM, PeripheralsArticle coming
- MEMS Sensor Interface: Capacitive, ResistiveArticle coming
- MIPI DPHY Termination and PCB DesignArticle coming
- MIPI DSI / CSI-2 Receiver Interface DesignArticle coming
- Memory Interface: External SRAM, HyperRAMArticle coming
- Mixed-Signal IC Evaluation Board DesignArticle coming
- Multi-MCU Communication: CAN, SPI, I2CArticle coming
- NAND Flash Parallel Interface LayoutArticle coming
- Noise Budget Allocation in Analog Signal ChainArticle coming
- Op-Amp GBW, Slew Rate, CMRR, PSRR SpecsArticle coming
- Op-Amp Inverting and Non-Inverting ConfigurationArticle coming
- Open-Collector / Open-Drain Pull-Up DesignArticle coming
- Optical Sensor Circuit: Photodiode, PhototransistorArticle coming
- PCB-Level EMI in Analog Sensor ChainsArticle coming
- PCIe Root Complex to Endpoint Board DesignArticle coming
- Peak Detector and Sample-and-Hold CircuitArticle coming
- Precision Current Source: PTAT, AdjustableArticle coming
- Precision Rectifier: Half-Wave, Full-WaveArticle coming
- Pressure Sensor Wheatstone Bridge AmplifierArticle coming
- Programmable Gain Amplifier (PGA) DesignArticle coming
- RF-Capable PCB for Analog ChainArticle coming
- RISC-V SoC Hardware Bring-Up MethodologyArticle coming
- RS-232 Level Shifter Circuit DesignArticle coming
- RS-485 Transceiver and Fail-Safe ResistorsArticle coming
- Rail-to-Rail Op-Amp Selection for Low-VoltageArticle coming
- Real-Time Clock (RTC) Circuit with CrystalArticle coming
- Reset Circuit: External Supervisor, Brown-OutArticle coming
- SAR ADC Reference Voltage DecouplingArticle coming
- SDRAM / DDR Interface Routing and TerminationArticle coming
- Schmitt Trigger and Hysteresis DesignArticle coming
- Series Termination and Parallel TerminationArticle coming
- Shield Trace and Guard Ring for AnalogArticle coming
- Single-Ended to Differential ConversionArticle coming
- SoC Platform: NXP, STM32, Nordic, ESP32Article coming
- Switched-Mode Noise on Analog Supply MitigationArticle coming
- Thermocouple and RTD Signal ConditioningArticle coming
- USB ESD Protection: D+ and D- LinesArticle coming
- USB Type-C with CC Logic and PD ControllerArticle coming
- Voltage Comparator: Open Drain vs. Push-PullArticle coming
- Voltage-to-Current (Howland) ConverterArticle coming
- Window Comparator Design and ApplicationArticle coming
Senior Engineer· 0 of 40
- 48V Mild Hybrid Automotive Power DesignArticle coming
- Battery Charger IC: CC/CV Charging AlgorithmArticle coming
- Battery Cycle Life vs. Charge Rate Trade-offArticle coming
- Buck Converter Layout for Minimal EMIArticle coming
- Bypass Capacitor: ESR, ESL vs. FrequencyArticle coming
- Cell Balancing: Passive vs. Active TopologyArticle coming
- Copper Fill and Thermal Via for Power DissipationArticle coming
- Current Probe and Rogowski Coil MeasurementArticle coming
- EMI Filter Optimization with Pre-ComplianceArticle coming
- EMI from Switching Regulator: Radiated, ConductedArticle coming
- EV Battery Pack: Module, BMS, ContactorArticle coming
- Energy Harvesting HW: Solar, TEG, PiezoArticle coming
- Fast Charging: USB PD 3.1, Qualcomm QC 5.0Article coming
- Fuel Gauge IC: Coulomb Counter vs. Voltage-BasedArticle coming
- GaN Fast Charger Module (65W, 140W) DesignArticle coming
- High-Voltage Safety Isolation for BMS (>60V)Article coming
- Hot-Swap Controller for Live InsertionArticle coming
- Input EMI Filter: Common-Mode ChokeArticle coming
- LDO Bypass Capacitor CIN / COUT RequirementsArticle coming
- LDO Voltage Regulator Selection and StabilityArticle coming
- Li-Ion Battery Protection IC (OVP, UVP, OCP)Article coming
- Multi-Cell BMS Architecture: 2S, 4S, 10SArticle coming
- OR-ing Circuit for Redundant Power SuppliesArticle coming
- PCB Power Rail Decoupling: Bulk, Mid-Freq, HFArticle coming
- PDN Impedance Target from IC DatasheetArticle coming
- PMIC Integration: Multi-Rail Power ManagementArticle coming
- Power Architecture Review and System BudgetArticle coming
- Power Efficiency Measurement (E-Load + PA)Article coming
- Power Path Management for Battery-PoweredArticle coming
- Power Sequencing Circuit: Supervisor, MOSFETArticle coming
- Power-Good Signal Usage and MonitoringArticle coming
- Reverse Polarity Protection: P-MOSFETArticle coming
- Sequencing Requirements for SoC/FPGA RailsArticle coming
- Soft-Start Circuit to Limit Inrush CurrentArticle coming
- Switching Regulator Component SelectionArticle coming
- TVS and MOV for Surge ProtectionArticle coming
- Thermal Management for Charging ICArticle coming
- USB PD Negotiation: CC Pin, VBUS ProfilesArticle coming
- USB Power Delivery (PD) Sink ControllerArticle coming
- Wireless Charging (Qi 1.3 / Qi 2.0) Coil and ICArticle coming
Staff Engineer· 0 of 40
- AOI (Automated Optical Inspection) SetupArticle coming
- Active Differential Probe UsageArticle coming
- BERT (Bit Error Rate Tester) for SerDesArticle coming
- Boundary Scan Test (JTAG) for PCB DebugArticle coming
- Burn-In Test Rack Design and OperationArticle coming
- CAPA (Corrective and Preventive Action)Article coming
- Current Probe: Clamp, Rogowski, Coaxial ShuntArticle coming
- De-Embedding Fixture Effects from VNAArticle coming
- EFT/Burst Generator: IEC 61000-4-4 UsageArticle coming
- ESD Simulator: IEC 61000-4-2 Test SetupArticle coming
- Environmental Screening: Temp Cycling, HumidityArticle coming
- Eye Diagram Mask Test on OscilloscopeArticle coming
- FMEA (Failure Modes and Effects Analysis)Article coming
- Failure Analysis: SEM, FIB, TEM TechniquesArticle coming
- Flying Probe Test Setup and CoverageArticle coming
- Functional Test Fixture DesignArticle coming
- HW Failure Investigation and Root Cause AnalysisArticle coming
- ICT (In-Circuit Test) Fixture DesignArticle coming
- In-Circuit Debugger: JTAG, SWD, cJTAGArticle coming
- Incoming Quality Control (IQC) for ComponentsArticle coming
- J-Link and OpenOCD Usage for FW DebugArticle coming
- LCR Meter for Impedance MeasurementArticle coming
- LISN (Line Impedance Stabilization Network)Article coming
- Logic Analyzer: State and Timing ModeArticle coming
- Near-Field EMI Probe Set (H-field, E-field)Article coming
- Oscilloscope Probe: 1x vs. 10x vs. 100xArticle coming
- Oscilloscope: Bandwidth, Sample Rate, Memory DepthArticle coming
- Power Integrity: PDN Analyzer (Picotest)Article coming
- Protocol Decoder: UART, SPI, I2C, CAN, USBArticle coming
- Qualification: Vibration, Shock, Altitude TestsArticle coming
- Reliability Testing: HALT, HASS, HAST, THBArticle coming
- Saleae Logic Pro: Analog + Digital CombinedArticle coming
- Spectrum Analyzer: RBW, VBW, Span SettingArticle coming
- Surge Generator: IEC 61000-4-5 Test SetupArticle coming
- TDR for Impedance Profile MeasurementArticle coming
- Thermal Camera: Hot-Spot IdentificationArticle coming
- Thermal Chamber: -40C to +85C ProfilingArticle coming
- VNA TRL / SOLT Calibration ProcedureArticle coming
- Vector Network Analyzer (VNA) Basics: S11, S21Article coming
- X-Ray Inspection for BGA Solder JointsArticle coming
Distinguished Engineer· 0 of 40
- Backplane Connector and High-Density InterfaceArticle coming
- Board-to-Board Connector Stack HeightArticle coming
- Cable Harness Routing and ShieldingArticle coming
- Carrier Board Design for SoM (Jetson, CM4)Article coming
- Chiplet-Based System HW DesignArticle coming
- Design Input / Design Output TraceabilityArticle coming
- Design for Manufacturing (DFM) ReviewArticle coming
- Design for Reliability (DFR): HALT StrategyArticle coming
- Design for Test (DFT) Planning at System LevelArticle coming
- Digital Twin for HW System ValidationArticle coming
- EMC Architecture: Filtering, Shielding, GroundingArticle coming
- FPGA + CPU Heterogeneous Platform DesignArticle coming
- Fan and Blower Selection: Airflow CalculationArticle coming
- Functional Safety Architecture: ISO 26262Article coming
- HW Architecture for Space (Rad-Hard, EEE)Article coming
- HW Security Architecture: TPM, Secure ElementArticle coming
- HW-SW Co-Design: Timing Closure for HWArticle coming
- Hardware Architecture Review Process (HAR)Article coming
- Heat Pipe and Vapor Chamber in SystemArticle coming
- Hot-Swap and Live-Insert Board ArchitectureArticle coming
- Interface Control Document (ICD) for BoardsArticle coming
- Multi-Board System Interconnect DesignArticle coming
- Multi-Generation Platform Architecture PlanningArticle coming
- Open Hardware Standards: OCP, ODSA, OIFArticle coming
- PCIe Backplane Design for Multi-BoardArticle coming
- Platform Reuse and Scalability StrategyArticle coming
- Prototype Build: EVT, DVT, PVT MilestonesArticle coming
- Redundancy Architecture: N+1, 2N Power SupplyArticle coming
- Requirements Capture: MRD > HRD > SchematicArticle coming
- SoM vs. Custom PCB Trade-off AnalysisArticle coming
- Supplier Selection: EMS, CM, ODM ComparisonArticle coming
- Sustainability: Low-Power Architecture, RoHSArticle coming
- System Block Diagram: Top-Down DesignArticle coming
- System Enclosure: Al vs. Steel ShieldingArticle coming
- System Grounding: Single-Point vs. Multi-PointArticle coming
- System Power Budget: Steady-State and PeakArticle coming
- Technology Roadmap for HW PlatformArticle coming
- Thermal Budget: Junction Temperature TargetArticle coming
- Thermal Enclosure: Conduction vs. ConvectionArticle coming
- Water Cooling Block for High-Power HWArticle coming