Embedded Systems
Core embedded software engineering: microcontroller programming, peripheral drivers, and system bring-up.
400 topics · 39 with articles
Intern Engineer· 40
- ADC Key Specs: Resolution, ENOB, INL, DNL, SNR
- ADC Operation: SAR, Successive Approximation, Reference
- Analog Comparator: Hysteresis and Wake-Up Application
- CAN Controller: Arbitration, Frame Format, Bit Timing
- CPU Core: ALU, Control Unit, Registers, PC, SP
- Clock System: Internal RC, External Crystal, PLL
- DAC Output: Voltage Mode, Current Mode, Settling Time
- DMA Controller: Channel, Priority, Circular, Double-Buffer
- Datasheet Reading: Block Diagram, Pinout, Electrical Specs
- Debugging Basics: Breakpoint, Watch, Step, Memory View
- Development Board: Arduino, Discovery, Nucleo, DevKit
- Flash and RAM Memory Organization in MCU
- GPIO Alternate Function and Peripheral Multiplexing
- GPIO Configuration: Input, Output, Open-Drain, Pull-Up/Down
- I2C Peripheral: Address, ACK, Clock Stretching, Multi-Master
- IDE Options: STM32CubeIDE, SEGGER Embedded Studio, VS Code
- Interrupt Controller Basics: IRQ, Priority, Masking
- Interrupt Service Routine (ISR): Latency and Reentrance
- Interrupt Vector Table: Address, Handler, Priority
- MCU Errata: Known Silicon Bugs and Workarounds
- MCU Family Overview: STM32, nRF52, ESP32, RP2040, PIC
- MCU Selection Criteria: Core, Speed, Flash, RAM, Peripherals
- Microcontroller vs. Microprocessor vs. SoC Differences
- NVIC (Nested Vectored Interrupt Controller) Configuration
- Nested Interrupts and Interrupt Priority Levels
- PWM Generation: Period, Duty Cycle, Dead-Time
- Polling vs. Interrupt-Driven I/O Trade-offs
- Power Management: Sleep, Stop, Standby Mode Selection
- Programming Interfaces: JTAG, SWD, UART ISP, USB DFU
- RTC (Real-Time Clock): Calendar, Alarm, Battery Backup
- Reference Manual vs. Datasheet vs. Application Note
- Register-Level Programming vs. HAL/LL Driver Comparison
- Reset Sources: Power-On, Brown-Out, Watchdog, Software
- SPI Peripheral: Master/Slave, CPOL, CPHA, NSS Control
- Timer / Counter: Modes (Free-Run, Output Compare, Input Capture)
- Toolchain Setup: Compiler (GCC-ARM), Linker, Debugger
- UART/USART: Baud Rate, Parity, Stop Bits, Flow Control
- USB Device Controller: Endpoint, Descriptor, Enumeration
- Von Neumann vs. Harvard Architecture Comparison
- Watchdog Timer (WDT): Independent and Window WDT
Junior Engineer· 40
- 1-Wire Protocol: Parasite Power, Search Algorithm
- CAN 2.0A and 2.0B Frame: SOF, ID, DLC, Data, CRC
- CAN Bit Timing: Propagation Segment, Phase Segments
- CAN Bus Termination: 120 Ω and Split Termination
- CAN Error Frames: Active, Passive, Bus-Off State Machine
- CAN FD: Higher Baud Rate, Larger Payload (64 Bytes)
- Ethernet: PHY Layer, MII/RMII Interface, Auto-Negotiation
- I2C Bus Recovery: Stuck SDA / SCL Procedure
- I2C Clock Stretching and Multi-Master Arbitration
- I2C Protocol: 7-Bit and 10-Bit Addressing
- I2C Pull-Up Resistor Calculation: Rise Time vs. Bus Cap
- I2S / PCM Audio Interface: BCLK, LRCLK, SDATA
- LIN Bus: Break Field, Sync, ID, Data, Checksum
- LIN Master/Slave Schedule Table and Frame Slots
- MDIO: PHY Register Access and Configuration
- MIPI CSI-2: Lane Protocol for Camera Sensor Data
- MIPI DSI: Display Serial Interface Packet Structure
- MIPI I3C: Multi-Drop, Higher Speed Successor to I2C
- Modbus ASCII: Framing and LRC Check
- Modbus RTU: Function Codes, CRC Calculation
- PDM (Pulse Density Modulation) Microphone Interface
- PMBus: Power Management Commands over SMBus
- Quad-SPI (QSPI) and Octo-SPI for Flash Access
- RS-232 Voltage Levels and MAX232 Level Shifter
- RS-485 Half-Duplex Differential Bus: Drive Enable Timing
- RS-485 Termination Resistor and Fail-Safe Bias
- SMBus: Alert Line, Packet Error Check (PEC)
- SPI DMA Transfer for High-Speed Peripherals
- SPI Full-Duplex vs. Half-Duplex Operation
- SPI Multi-Slave: NSS Hardware vs. Software Select
- SPI Protocol: Clock Polarity (CPOL) and Phase (CPHA) Modes
- SpaceWire / MIL-STD-1553: Avionics Bus Protocols
- UART Baud Rate Error Calculation and Tolerance
- UART Frame Format: Start, Data, Parity, Stop Bits
- UART Hardware Flow Control: RTS/CTS Lines
- USB CDC (Virtual COM Port): ACM Subclass
- USB DFU Class: Firmware Upgrade over USB
- USB Full-Speed (12 Mbps): Enumeration and Descriptors
- USB HID Class: Report Descriptor, Boot Protocol
- USB MSC (Mass Storage): SCSI Command Set over USB
Middle Engineer· 120
- AHB-Lite: Single-Layer Master, Burst Transactions
- APB Bridge: Low-Bandwidth Peripheral Access
- ARM AMBA Bus: AHB-Lite, APB, AXI Interface Overview
- ARM CMSIS: Core, DSP, NN, RTOS, Driver Layers
- ARM Cortex-M Family: M0, M0+, M3, M4, M7, M23, M33, M55
- AUTOSAR OS: Task, ISR, Alarm, Resource, Schedule Table
- Binary Semaphore: ISR-to-Task Synchronization Pattern
- Bit-Banding: Atomic Single-Bit Read-Write in SRAM/Peripheral
- Bus Matrix: Multi-Master, Multi-Slave Concurrent Access
- CMSIS-DSP: Fixed-Point and Floating-Point Signal Functions
- CMSIS-NN: Neural Network Kernels for Cortex-M Inference
- CPU Load Measurement: DWT CYCCNT Idle vs. Active
- Cache Coherency Issues with DMA and Shared Memory
- Cache Maintenance Operations: Invalidate, Clean, Flush
- CoreSight Components: ETM, ITM, DWT, MTB, TPIU
- CoreSight Debug Architecture: DAP, SW-DP, JTAG-DP
- Cortex-M Exception Priority: Fixed and Configurable
- Cortex-M Memory Map: Code, SRAM, Peripheral, PPB Regions
- Cortex-M Power Modes: Sleep, Deep Sleep, WFI, WFE
- Cortex-M Security Extension (Cortex-M23/M33): SAU, IDAU
- Cortex-M4/M33 DSP Extensions: SIMD, Saturating Arithmetic
- Cortex-M55 Helium (M-Profile Vector Extension, MVE)
- Cortex-M7 Cache: 4-Way Set-Associative I-Cache and D-Cache
- Counting Semaphore: Resource Pool Management
- DWT: Cycle Counter (CYCCNT), Data Watchpoints
- Deadline-Monotonic and EDF Scheduling Algorithms
- ESP-IDF: FreeRTOS Base, Partition Table, NVS Flash
- ESP32 Architecture: Xtensa LX6, Wi-Fi, BLE, PSRAM
- ESP32 Wi-Fi: Station, SoftAP, WPA3, Power-Save Modes
- ESP32-C3 / C6: RISC-V Core, Wi-Fi 6, BLE 5.3
- ETM Instruction Trace: Cycle-Accurate Execution Recording
- Event-Driven Wake-Up: SEV and WFE Instruction Pair
- Exception Entry and Return: EXC_RETURN Value Encoding
- Exception Model: Reset, NMI, HardFault, MemManage, BusFault
- FPU (Cortex-M4/M7/M33): Single-Precision IEEE 754
- FPU Lazy Stacking and Context Save on Interrupt Entry
- FreeRTOS Event Groups: xEventGroupSetBits, WaitBits
- FreeRTOS Queue: xQueueCreate, Send, Receive, Peek
- FreeRTOS Task Creation: xTaskCreate, Stack Size, Priority
- FreeRTOS Trace: Tracealyzer Integration and Timeline
- FreeRTOS+FAT: File System for Embedded Storage
- FreeRTOS+TCP: Lightweight TCP/IP Stack Integration
- Heap Memory Management: heap_1 to heap_5 Comparison
- ITM Stimulus Ports: Printf-Style Trace Without Halt
- Idle Task and Idle Hook: Low-Power or Background Work
- MPU Region Configuration: Base, Size, Access Permissions
- Memory Protection Unit (MPU): Region, Attributes, Permissions
- Message Buffer: Variable-Length Message Passing
- Mutex: Mutual Exclusion and Priority Inheritance
- NVIC: Priority Grouping, Preemption, and Sub-Priority
- Non-Secure Callable (NSC) Function Gateway
- Nordic Matter (Thread/BLE) and Apple HomeKit Integration
- OSEK/VDX OS: Conformance Classes (BCC1, ECC2)
- Operating Modes: Thread Mode and Handler Mode
- PIO (Programmable I/O): State Machine for Custom Protocols
- POSIX PSE51 Profile: Subset for Real-Time Embedded
- Preemptive Scheduling: Highest Ready Task Runs
- Priority Ceiling Protocol: Alternative to Inheritance
- Priority Inversion Problem and Priority Inheritance Solution
- Privilege Levels: Privileged and Unprivileged Execution
- Processor Registers: R0–R12, SP (R13), LR (R14), PC (R15)
- Program Status Register: APSR, IPSR, EPSR (xPSR)
- Queue Sets: Blocking on Multiple Queues Simultaneously
- RP2040: Dual Cortex-M0+, PIO State Machine, USB
- RTOS Concepts: Task, Scheduler, Context Switch, TCB
- Rate-Monotonic Scheduling (RMS) Schedulability Test
- Recursive Mutex: Re-entrant Locking for Same Task
- Round-Robin Scheduling: Equal Priority Time-Slicing
- STM32 ADC: Oversampling, Injected, Regular, DMA Chain
- STM32 Alternate Function Mapping (AFR Registers)
- STM32 Clock Tree: HSI, HSE, LSI, LSE, PLL Configuration
- STM32 Crypto Accelerator: AES-128/192/256, HASH, TRNG
- STM32 DMA: Stream, Channel, Priority, FIFO, Burst
- STM32 FDCAN: CAN FD Protocol, Rx FIFO, Tx Event
- STM32 Family Overview: F0–F7, G0–G4, H7, L0–L5, U5, WB
- STM32 Flash: Dual Bank, PCROP, WRP, OTP Sector
- STM32 GPIO Registers: MODER, OTYPER, OSPEEDR, PUPDR, IDR, ODR
- STM32 HAL Library: Init, DeInit, Poll, IT, DMA Functions
- STM32 LL (Low-Layer) Driver: Register-Level Macros
- STM32 LPTIM: Low-Power Timer Wake from Standby
- STM32 LPUART: Low-Power UART Wake from Stop Mode
- STM32 RCC Register: System Clock Selection, AHB/APB Dividers
- STM32 RTC: Calendar, Alarm, Tamper, Timestamp
- STM32 SBSFU: Secure Boot and Firmware Update Framework
- STM32 TIM Advanced: PWM, Input Capture, Encoder Mode
- STM32 USB Device Library: CDC, HID, MSC Stack
- STM32CubeIDE: Debug, Live Watch, SWV Timeline View
- STM32CubeMX: Pin Configurator, Clock Tree, Code Generator
- STM32WB CoProcessor Table (CPT): RF Stack Update
- STM32WB: BLE + 802.15.4 Dual-Core Architecture
- Software Timer: xTimerCreate, Start, Stop, Reset, Change Period
- Stack Overflow Detection: Stack Canary and High-Water Mark
- Stack Pointer Types: MSP (Main) and PSP (Process)
- Stream Buffer: Byte-Level ISR-to-Task Data Stream
- SysTick Timer: 24-bit Down-Counter, RTOS Tick Source
- Task States: Running, Ready, Blocked, Suspended, Deleted
- ThreadX / Azure RTOS: Preemption-Threshold Feature
- Thumb-2 Instruction Set: 16-bit and 32-bit Mixed Encoding
- Tick Hook: High-Frequency Periodic Callback
- TrustZone-M: Secure and Non-Secure World Partitioning
- Worst-Case Execution Time (WCET) Analysis Techniques
- Zephyr Devicetree: HW Description, Bindings, Overlays
- Zephyr Kconfig: Build-Time Configuration System
- Zephyr Message Queue and Mailbox
- Zephyr Power Management: Device and System PM
- Zephyr RTOS Architecture: Kernel, Subsystems, Drivers
- Zephyr RTOS on nRF52: Board Definition, DTS, Devicetree
- Zephyr Synchronization: k_sem, k_mutex, k_condvar
- Zephyr Threads: K_THREAD_DEFINE, Stack, Priority
- Zephyr Work Queue: Deferred Processing from ISR
- nRF5 SDK vs. nRF Connect SDK (Zephyr-Based)
- nRF52 BLE Advertising: Extended, Periodic Advertising
- nRF52 BLE Connection: Parameters, PHY, Data Length Ext.
- nRF52 Bootloader: Open Bootloader and DFU over BLE/UART
- nRF52 GATT Profile Design: Service, Characteristic, Descriptor
- nRF52 Power Profiler Kit (PPK2): Current Measurement
- nRF52 Security Manager: Pairing, Bonding, LE Secure Connections
- nRF52 SoftDevice: BLE Protocol Stack Architecture
- nRF52 UART, SPI, I2C, PDM, I2S Peripheral (EasyDMA)
- nRF52840: ARM Cortex-M4, BLE 5.3, 802.15.4, USB
Senior Engineer· 80
- A/B Partition Layout: Active and Backup Firmware Slots
- Anti-Rollback Counter: Monotonic NVM Counter in eFuse/OTP
- Bootloader Basics: Reset Handler Jump to Application
- Bootloader Magic Number: Boot Decision Logic
- Buildroot: Board Configuration, Package, BR2_PACKAGE
- CRC / SHA-256 Firmware Integrity Check in Bootloader
- Character Device Driver: file_operations, cdev_add
- Compressed Firmware Storage: LZ4, zlib Decompression
- Copy Table: LMA to VMA Data Initialization
- DMA Engine API: dmaengine_prep_slave_sg, dma_async_issue
- Debugfs: Kernel Debug Information Export
- Device Tree (DTS): Node, Property, Compatible String
- Device Tree Bindings: Documenting Compatible Strings
- Device Tree Overlay (DTBO): Dynamic HW Description
- Differential OTA Update: Binary Patch (bsdiff, xdelta)
- EEPROM Emulation in Internal Flash (STM32 EEPROM Emul)
- ELF File Structure: .text, .data, .bss, .rodata Sections
- Embedded Linux Debug: KGDB, JTAG, ftrace, perf
- External SPI EEPROM / NOR Flash Driver Design
- FIT Image (Flattened Image Tree): Multi-Component Boot
- Factory Reset and Safe Firmware Fallback Mechanism
- FatFS: FAT12/16/32 for SD Card and USB Mass Storage
- Flash Erase-Write-Read Cycle and Endurance Limits
- Heap Fragmentation: First-Fit, Best-Fit, dlmalloc
- Hypervisor for Mixed-Criticality: Jailhouse, Xen on ARM
- In-Application Programming (IAP) via UART / CAN
- Kernel Configuration: menuconfig, defconfig, .config
- Kernel Hardening: ASLR, Stack Canary, CONFIG_FORTIFY
- Kernel Memory: kmalloc, vmalloc, DMA Coherent Alloc
- Kernel Module: init_module, cleanup_module, Makefile
- Kernel Timer: hrtimer vs. timer_list Comparison
- Key Provisioning: Certificate Injection at Manufacturing
- Linker Script (.ld): Memory Regions, Sections, Symbols
- Linux Boot Sequence: ROM → SPL → U-Boot → Kernel → Init
- Linux CAN SocketCAN: CAN Raw Socket, can_frame
- Linux GPIO Subsystem: gpiod_get, gpiod_direction_output
- Linux I2C Driver: i2c_driver, i2c_smbus_read_byte_data
- Linux IIO (Industrial I/O): ADC, DAC, IMU Subsystem
- Linux Input Subsystem: input_dev, input_report_key
- Linux Interrupt: request_irq, free_irq, IRQ Threading
- Linux Power Management: Runtime PM, System Suspend/Resume
- Linux Regulator Framework: voltage-regulator Driver
- Linux SPI Driver: spi_driver, spi_transfer, spi_message
- Linux Security Modules: SELinux, AppArmor Policy
- Linux UART (TTY) Driver: uart_driver, uart_ops
- LittleFS: Log-Structured, Power-Fail-Safe Filesystem
- MCUboot: Open-Source Bootloader Configuration (Zephyr)
- Memory Map Analysis: .map File Symbol Locations
- Memory Protection Unit (MPU): Region Isolation and Privilege
- Mmap for Zero-Copy: remap_pfn_range, vm_fault
- NAND Flash Controller: Bad Block Management, ECC
- OPTEE-OS: Trusted Execution Environment on Cortex-A
- OTA Update Architecture: Download, Verify, Swap, Reboot
- OpenWrt for Embedded Networking Devices
- Pinctrl Subsystem: Pin Mux and Pin Configuration
- Platform Driver Model: probe, remove, of_match_table
- Power-Fail Safe Flash Write: Atomic Page Update Pattern
- QSPI Flash XIP: Memory-Mapped Mode Configuration
- SPIFFS (SPI Flash File System): Deprecated vs. LittleFS
- Secure Boot on Embedded Linux: U-Boot + FIT + IMA/EVM
- Secure Boot: ECDSA / RSA Signature Verification Chain
- Stack Size Calculation: Worst-Case Interrupt Nesting
- Stack and Heap Layout: Growth Direction, Size Config
- Startup File: Reset_Handler, __libc_init_array, main Call
- Static Memory Allocation vs. Dynamic Allocation in Embedded
- Sysfs Interface: kobject, kset, Attribute Files
- Threaded IRQ: request_threaded_irq for Long ISR Handlers
- Trusted Firmware-M (TF-M): BL2 Secure Boot Integration
- U-Boot Commands: fatload, bootz, booti, tftp, nand
- U-Boot Verified Boot: FIT Image Signature and Hash
- U-Boot: Environment Variables, bootcmd, bootargs
- USB DFU Bootloader: DFU Class, Alternate Settings
- User-Kernel Space: copy_to_user, copy_from_user
- Wear Leveling: Static, Dynamic, Global Algorithms
- Workqueue: schedule_work, INIT_WORK, Delayed Work
- XIP (Execute-in-Place) from External NOR Flash
- Yocto Image Customization: IMAGE_INSTALL, DISTRO_FEATURES
- Yocto Project: Layer, Recipe (.bb), Bitbake Commands
- eFuse / OTP Burning for Device Identity and Config Fuse
- ioctl Interface: unlocked_ioctl, compat_ioctl Design
Lead Engineer· 40
- Anti-Tamper Design: Mesh, Voltage Glitch, Temperature Sensor
- Attestation: Device Identity and Quote Verification
- CERT C Secure Coding Standard: Key Rules (INT, MEM, STR)
- CWE (Common Weakness Enumeration) for Embedded
- Code Coverage Criteria: Statement, Branch, MC/DC
- Cyclomatic Complexity: McCabe Metric and Limit
- DO-178C: Software Levels (DAL A–E) for Aviation
- DTLS 1.3: Datagram Transport for CoAP and MQTT-SN
- Dynamic Analysis: Valgrind, AddressSanitizer, MemorySanitizer
- EN 50128: Railway Software Safety Standard
- EU Cyber Resilience Act (CRA): Embedded Product Requirements
- FIPS 140-3: Cryptographic Module Validation Levels 1–4
- FMEDA: Failure Modes, Effects, and Diagnostic Analysis
- Failure Mode and Effect Analysis (FMEA) for Software
- Fault Injection Defense: Redundant Execution, Diversity
- Fault Tree Analysis (FTA): Top Event, AND/OR Gates
- Firmware Extraction and Reverse Engineering Defense
- Formal Methods for Safety: Abstract Interpretation, Coq, SPARK Ada
- Hardware Security Module (HSM) Driver: PKCS#11 API
- IEC 61508: Functional Safety Lifecycle (SIL 1–4)
- IEC 61511: Process Industry Safety (SIL and PFD)
- IEC 62304: Medical Device Software Lifecycle (Class A/B/C)
- IEC 62443-4-2: Component Security Level (SL1–SL4)
- ISO 26262 Part 6: Software Requirements and ASIL Decomposition
- ISO 26262: Automotive Functional Safety (ASIL A–D)
- ISO/SAE 21434: Automotive Cybersecurity Engineering
- MC/DC (Modified Condition/Decision Coverage) for DAL A
- MISRA-C Rule Examples: No Dynamic Allocation, No Recursion
- MISRA-C:2012: Mandatory, Required, Advisory Rule Categories
- Penetration Testing Embedded: UART, JTAG, JTAG Lock Bypass
- Post-Quantum Cryptography on MCU: Kyber-512, Dilithium
- SBOM (Software Bill of Materials): CycloneDX for Embedded
- Secure Boot Chain: ROM BL0 → BL1 → BL2 → Kernel
- Secure Coding: Buffer Overflow, Integer Overflow Prevention
- Secure Element Integration: ATECC608B, SE050 API
- Side-Channel Countermeasures: Masking, Blinding, Constant-Time
- Static Analysis Tools: PC-lint Plus, Polyspace, Klocwork, Helix QAC
- TLS 1.3 on MCU: mbedTLS, wolfSSL, Mbed TLS Handshake
- Trusted Execution Environment (TEE): TrustZone-M, TrustZone-A
- UNECE WP.29 R155 and R156: Vehicle Cyber and OTA Regulation
Staff Engineer· 40
- Asymmetric Multi-Processing (AMP): Cortex-A + Cortex-M
- Branch Prediction: Static, Dynamic (2-bit Saturating Counter)
- Bus Interconnect: AHB Matrix, AXI Crossbar Performance
- CPU Affinity: taskset, isolcpus for Real-Time Task Isolation
- CPU Performance Metrics: MIPS, CoreMark, DMIPS
- Cache Architecture: I-Cache, D-Cache, Unified L2 Cache
- Cache Associativity: Direct-Mapped, 2-Way, 4-Way, Fully
- Cache Coherence in Multi-Core: MESI Protocol on ARM
- Cache Prefetching: Hardware and Software Prefetch Instructions
- Cache Write Policies: Write-Back vs. Write-Through
- Co-Processing: FPGA Offload for MCU Acceleration
- DMA Performance: Burst Length, FIFO Threshold Optimization
- DVFS (Dynamic Voltage Frequency Scaling) Linux cpufreq
- ETM Trace and Instruction-Level Profiling
- Embedded Hypervisor: Jailhouse, XEN, bhyve on ARM
- Execution Profiling: Gprof, Callgrind, Tracy
- FPGA Soft-Core CPU: MicroBlaze, NIOS II, PicoRV32
- Functional Safety Architectural Patterns: Lockstep, Safety Island
- Heterogeneous SoC: CPU + DSP + GPU + NPU Architecture
- Latency Measurement: Cyclictest, Latency Histogram
- Lock-Free Programming: Atomic Operations, Memory Ordering
- MMU (Memory Management Unit): Page Table Walk, ASID
- Memory Bandwidth and Latency Profiling: ARM DS-5, perf
- Memory Barriers: DMB, DSB, ISB on ARM Architecture
- OpenAMP: Remoteproc and RPMsg for AMP Communication
- Out-of-Order Execution and Register Renaming
- Pipeline Hazards: Data Hazard, Control Hazard, Structural
- Pipeline Stages: Fetch, Decode, Execute, Memory, Write-Back
- Power Profiling: J-Link Energy, PPK2, Advanced Energy Monitor
- RISC-V Architecture: ISA Base (RV32I) and Extensions (M, A, F, C)
- RISC-V Physical Memory Protection (PMP) Configuration
- RISC-V Privileged Spec: Machine, Supervisor, User Mode
- RISC-V Vector Extension (RVV): SIMD for Embedded DSP
- Real-Time Performance on Embedded Linux: PREEMPT_RT Patch
- SoC Platform Selection: NXP i.MX, Raspberry Pi CM4, Jetson
- Superscalar Execution: Multiple Issue Units in Parallel
- Symmetric Multi-Processing (SMP): Linux on Quad-Core A55
- TLB (Translation Lookaside Buffer): Virtual-to-Physical Map
- Thermal Throttling: CPU Frequency Reduction on Overheat
- Zephyr RTOS on RISC-V: Build and Boot Process
Distinguished Engineer· 40
- Anomaly Detection on MCU: Autoencoder and PCA Approach
- Audio Classification: Mel-Spectrogram + CNN on Cortex-M
- CMSIS-NN: ARM-Optimized Kernel Library for Cortex-M
- Camera Interface: DVP (Digital Video Port) and MIPI CSI-2
- Color Space Conversion: RGB888 → RGB565 → Grayscale
- Continual / Incremental Learning on Embedded Devices
- EThos-U55 / U65: Arm ML Processor for Cortex-M Systems
- Edge AI Overview: Inference at the Device vs. Cloud
- Edge Impulse: Data Collection, Training, Deployment to MCU
- Embedded OpenCV: ARM Neon Optimization
- Face Detection on MCU: Haar Cascade, MobileNet-SSD
- Federated Learning on MCU: Privacy-Preserving On-Device
- Future Edge AI: RISC-V AI Extensions, Chiplet NPU Integration
- Gesture Recognition: IMU Data → TFLite Micro Inference
- Image Preprocessing on MCU: Resize, Crop, Normalize
- JPEG Decode on MCU: libjpeg-turbo, STM32 JPEG HW IP
- Keyword Spotting (KWS): DS-CNN on Cortex-M for Wake-Word
- Knowledge Distillation: Teacher-Student Model Compression
- MAX78000: Ultra-Low-Power CNN Accelerator
- MCU AI Frameworks: TensorFlow Lite Micro (TFLite Micro)
- MCU Inference Benchmarks: MLPerf Tiny Results
- Memory Optimization: Scratch Buffer, In-Place Operations
- Model Deployment Pipeline: CI/CD for Edge AI Models
- Model Pruning: Weight Magnitude, Structured vs. Unstructured
- NDP120 / NDP200: Syntiant Neural Decision Processor
- Neuromorphic Computing: Intel Loihi, BrainScaleS Basics
- ONNX Runtime for Embedded: Inference on Cortex-A
- OTA Update for AI Model: Delta Model Update Strategy
- Object Detection on MCU: YOLO-Nano, TinyYOLO
- OpenMV Cam: Machine Vision on STM32H7
- Operator Fusion: Reducing Memory and Compute Overhead
- Optical Flow on MCU: Lucas-Kanade for UAV Stabilization
- Person Detection: MobileNet-v2 on CMSIS-NN
- Post-Training Quantization: FP32 → INT8 Weight Conversion
- PyTorch Mobile: Lightweight Inference on Embedded Linux
- Quantization-Aware Training (QAT): Simulated Quantization
- STM32N6: Neural ART Accelerator on STM32
- TFLite Micro Workflow: Train → Convert → Quantize → Deploy
- Time-Series Classification: 1D CNN on Sensor Data
- TinyML Benchmarking: eAI, TinyMLPerf, MLCommons