Embedded SystemsStaffelite

Superscalar Execution: Multiple Issue Units in Parallel

Updated 18 May 2026

Contents & prerequisites

Prerequisites

Out-of-Order Execution and Register Renaming

Unlocks

Cache Architecture: I-Cache, D-Cache, Unified L2 Cache

Article in preparation

Superscalar Execution: Multiple Issue Units in Parallel

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Learning

PreviousSoC Platform Selection: NXP i.MX, Raspberry Pi CM4, Jetson NextSymmetric Multi-Processing (SMP): Linux on Quad-Core A55

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