Neuromorphic Computing: Intel Loihi, BrainScaleS Basics

Every embedded AI pipeline discussed elsewhere in this category — TFLite Micro, CMSIS-NN, Ethos-U55 — runs a synchronous, clocked, von Neumann model: weights and activations move through a data bus to a MAC array on every cycle, whether or not anything meaningful happened in the input. Neuromorphic computing rejects that premise. It asks what a processor looks like if it is built around spikes — sparse, asynchronous, event-driven signals — the way biological neurons actually communicate. For engineers working on always-on sensing, extreme power budgets, or adaptive control, understanding neuromorphic hardware matters because it is the one architecture class that can, in principle, decouple energy consumption from clock frequency and tie it instead to activity.

The Core Idea: Spiking Neural Networks (SNNs)

A conventional artificial neuron computes a weighted sum and pushes it through a static nonlinearity every inference cycle: y = f(Σ wᵢxᵢ). A spiking neuron instead integrates input current over time into a membrane potential V(t) and fires a discrete spike only when V(t) crosses a threshold V_th, after which it resets:

τ_m · dV/dt = -(V - V_rest) + R·I(t)
if V(t) ≥ V_th:  emit spike, V ← V_reset

This is the Leaky Integrate-and-Fire (LIF) model, the workhorse neuron of most neuromorphic chips. Two consequences follow directly:

• Information is encoded in spike timing/rate, not in a continuously-valued activation. A silent neuron costs (almost) nothing to evaluate.
• Computation is event-driven. A neuron/synapse only does work when a spike arrives, not on every global clock tick. Idle regions of the network — the common case for sparse, natural sensor data — draw near-zero dynamic power.

This is fundamentally different from quantized INT8 CNN inference on a Cortex-M: that workload still touches every weight every cycle, just with cheaper arithmetic. SNN hardware tries to avoid touching anything at all until a spike says otherwise.

Intel Loihi

Loihi (and Loihi 2) is Intel's research neuromorphic chip, built specifically to execute large SNNs efficiently.

Architecture:

• Many small neuromorphic cores per die (Loihi: 128 cores; Loihi 2: fewer, larger, more flexible cores), each simulating thousands of LIF-style neurons and their synapses locally in on-chip SRAM.
• Asynchronous mesh interconnect — cores communicate via spike messages (address-event representation, AER) routed on-chip, with no global clock synchronizing computation.
• On-chip learning: programmable synaptic plasticity rules (variants of Spike-Timing-Dependent Plasticity, STDP) let weights adapt locally, in hardware, without shipping data to a host for backprop.
• Loihi 2 adds programmable neuron models (not just fixed LIF), graded (multi-bit) spikes instead of binary events, and higher neuron/synapse density.

Why this matters practically: Intel's published results show Loihi-class chips achieving on the order of 10–100× lower energy per inference than a GPU/CPU baseline on sparse, temporal workloads (e.g., gesture recognition, olfactory sensing, optimization/search problems mapped onto spiking dynamics) — but the advantage is workload-dependent. On dense, regular tensor workloads (typical CNN inference), a conventional NPU with efficient INT8 MACs is usually still more energy-efficient per useful operation, because Loihi's benefit comes from exploiting sparsity and asynchrony, which dense matrix math doesn't have.

Loihi is programmed through Intel's Lava software framework, which lets you describe networks of interconnected processes (neurons, synapses, learning rules) that map onto the asynchronous hardware — a very different toolchain from TensorFlow/PyTorch graph export.

BrainScaleS

BrainScaleS (Heidelberg University, part of the EU Human Brain Project) takes a different implementation path: it is an analog/mixed-signal, accelerated-time neuromorphic system rather than a digital, biological-real-time one.

Key distinguishing properties:

Because membrane dynamics are implemented as literal analog circuits (an RC-like decay realized in silicon, not computed in digital logic), BrainScaleS neurons evolve in continuous time at wall-clock speeds far exceeding biology — useful for simulating long biological timescales (seconds to hours of brain activity) in a lab timeframe of seconds. The tradeoff is the classic analog one: device mismatch, temperature sensitivity, and calibration overhead replace the bit-exact repeatability of a digital design. This makes BrainScaleS primarily a neuroscience research and large-scale simulation tool, whereas Loihi is explicitly positioned as an embeddable, product-adjacent inference/learning accelerator.

Worked Comparison: Energy per Spike vs. Energy per MAC

To make the "event-driven" claim concrete, consider a small sensor-fusion network with 10,000 synapses, where on average only 2% are active (spiking) per timestep, evaluated at 1 kHz.

Conventional dense NPU (e.g., CMSIS-NN INT8 MAC array):

• Must evaluate all 10,000 synaptic weights every timestep regardless of activity.
• Operations/sec = 10,000 × 1,000 = 1×10⁷ MACs/s.
• At ~1 pJ/MAC (typical efficient INT8 MAC), power ≈ 1×10⁷ × 1×10⁻¹² J = 10 µW.

Event-driven neuromorphic core:

• Only active synapses consume energy: 2% × 10,000 = 200 active synapses/timestep.
• Operations/sec = 200 × 1,000 = 2×10⁵ spike-events/s.
• At ~10 pJ/synaptic event (higher per-event cost than a bare MAC, since it includes routing/AER overhead), power ≈ 2×10⁵ × 1×10⁻¹¹ J = 2 µW.

Check: even with a 10× higher per-event energy cost than the dense MAC (realistic for AER overhead), the 50× reduction in active operations (2% activity) still yields a net 5× power reduction (10 µW → 2 µW). This illustrates the actual crossover condition: neuromorphic hardware wins when sparsity × structural overhead ratio favors it — i.e., activity must be sparse enough to overcome the higher fixed cost per event. At 50% activity, the same math flips the result in favor of the dense NPU (5,000 events × 10 pJ = 50 µW ≫ dense's 10 µW), which is why neuromorphic chips are not a universal replacement for CNN accelerators.

Where This Fits in an Embedded Roadmap

• Not yet mainstream production silicon: Loihi and BrainScaleS are research/evaluation platforms (Intel Neuromorphic Research Community, EU research access), not parts you drop into a commercial BOM today — unlike Ethos-U55 or MAX78000, which ship in real products.
• Toolchains are immature and non-standard relative to TFLite Micro/ONNX flows: Lava (Loihi) and PyNN/BrainScaleS-specific stacks require learning spike-based network description, not just exporting a trained model.
• Best-fit workloads are those with genuinely sparse, temporal, event-based input: DVS (dynamic vision sensor) camera streams, always-on keyword/gesture triggers, olfactory/gas sensing, and combinatorial optimization problems reformulated as spiking dynamics — not standard image classification on dense frame data.
• Relevance for engineers today: understanding SNN principles positions you for next-generation ultra-low-power always-on sensing designs, and clarifies why conventional NPUs (Ethos-U, MAX78000) still dominate for dense CNN inference — the architectural tradeoff is sparsity-dependent, not a strict "neuromorphic is always better."

Key Takeaways

• Neuromorphic chips compute with spiking neurons (commonly LIF dynamics) that fire only above a threshold, making energy cost proportional to activity rather than clock cycles.
• Intel Loihi is a digital, asynchronous, many-core SNN chip with on-chip STDP learning, programmed via the Lava framework; it targets efficient edge inference/learning on sparse, temporal workloads.
• BrainScaleS is an analog/mixed-signal system that runs neuron dynamics in physical circuits at 1,000×–10,000× accelerated biological time, primarily for large-scale brain simulation research rather than deployed inference.
• The energy advantage of event-driven hardware over dense NPUs (CMSIS-NN, Ethos-U) depends on workload sparsity — the worked example shows the crossover shifts with activity ratio and per-event overhead, not a fixed multiplier.
• Neither platform is production-ready commercial silicon today; they matter for engineers as a preview of ultra-low-power, event-driven sensing architectures rather than a drop-in alternative to current MCU AI accelerators.