Camera Interface: DVP (Digital Video Port) and MIPI CSI-2

Every embedded vision pipeline starts at the sensor-to-SoC link, and that link is almost always one of two standards: parallel DVP or serial MIPI CSI-2. Choosing wrong — or misconfiguring timing/lane parameters — is why "the camera just shows garbage/green/half a frame" is one of the most common bring-up failures in embedded vision projects. Both interfaces carry the same conceptual payload (pixel data, line/frame syncs) but differ enormously in electrical implementation, achievable bandwidth, and pinout cost, which drives real BOM and PCB routing decisions.

DVP: The Parallel Legacy Interface

DVP (Digital Video Port, sometimes called "parallel camera interface") is the simplest possible camera bus: a byte- or word-wide data bus running in lockstep with dedicated sync signals, all single-ended, all referenced to a shared ground.

Typical DVP signal set:

Data is sampled on the SoC side on each PCLK edge while HREF is asserted; a VSYNC pulse delimits frames. A typical low-res sensor (e.g., a QVGA/VGA CMOS sensor) outputs 8-bit YUV422 or RGB565 over two PCLK cycles per pixel.

Bandwidth ceiling. DVP is fundamentally clock-rate limited because every bit is single-ended over a shared reference — signal integrity (crosstalk, ground bounce) caps practical PCLK around 24–48 MHz over a few centimeters of PCB/flex trace. For an 8-bit bus at 48 MHz:

Throughput = 8 bit × 48 MHz = 384 Mbit/s ≈ 48 MByte/s

At 2 bytes/pixel (YUV422), that's ~24 Mpixel/s — enough for VGA (640×480) at ~60 fps (640×480×60 ≈ 18.4 Mpixel/s) but nowhere near enough for 1080p30 (1920×1080×30 ≈ 62.2 Mpixel/s at 1 pixel/cycle-equivalent, i.e. ~124 MB/s at 2 B/pixel), which DVP essentially cannot do reliably.

Pin cost. An 8-bit DVP interface needs ~12–14 pins (8 data + PCLK + HREF + VSYNC + MCLK + power/reset), which matters on pin-constrained MCUs and drives up connector/flex-cable size in compact camera modules.

MIPI CSI-2: The Serial Differential Standard

CSI-2 (Camera Serial Interface 2), defined by the MIPI Alliance, replaces the wide single-ended bus with 1–4 (sometimes more) high-speed differential lane pairs plus one differential clock lane, running the D-PHY (or, in newer designs, C-PHY) physical layer.

Key structural differences from DVP:

• Differential signaling (like LVDS) rejects common-mode noise, allowing much higher per-pin data rates and longer/thinner cables than single-ended DVP.
• Packetized protocol: pixel data is wrapped in packets with a packet header (data type, word count, virtual channel), payload, and optional checksum/ECC — not a raw clocked bus.
• Low-power (LP) and high-speed (HS) states: lanes idle in a low-power mode between frames/lines and burst into HS mode only when transmitting, saving power versus DVP's continuously clocked bus.

D-PHY lane rates commonly run 1–2.5 Gbps per lane (up to ~4.5 Gbps in newer specs). For a 4-lane D-PHY link at 1.5 Gbps/lane:

Raw lane throughput = 4 × 1.5 Gbps = 6 Gbit/s

D-PHY high-speed transmission is NRZ — there is no 8b/10b-style line code, so no bit-stuffing overhead is incurred on the wire itself. The actual usable throughput loss instead comes from protocol-level overhead: packet header/footer bytes, sync codes, and ECC/checksum bytes attached to each packet, typically a small single-digit percentage of the raw lane rate for reasonably sized line lengths.

For a 1080p30 sensor at 10-bit RAW Bayer (before ISP demosaic):

Pixel rate = 1920 × 1080 × 30 = 62.2 Mpixel/s
Bit rate   = 62.2 Mpixel/s × 10 bit = 622 Mbit/s

622 Mbit/s comfortably fits inside a single lane at 1 Gbps, let alone 4 lanes — CSI-2 has an order of magnitude more headroom than DVP for the same resolution, which is exactly why every modern smartphone/embedded camera module (12 MP+, high frame rate, multi-camera) moved to CSI-2.

Data types. CSI-2 defines standard "data type" codes in the packet header so a single physical link can carry different payloads: RAW6/8/10/12/14 Bayer, YUV420/422, RGB888, and even generic/embedded non-image data (metadata lines). This is protocol-level flexibility DVP simply doesn't have — DVP's format is whatever the sensor's parallel output register says, fixed by wiring convention.

DVP vs. CSI-2: Side-by-Side

Worked Example: Choosing an Interface for a Person-Detection Camera

Suppose you're speccing a camera for an MCU running a MobileNet-based person detector at QVGA (320×240), grayscale/RGB565, targeting 15 fps.

Pixel rate = 320 × 240 × 15 = 1.152 Mpixel/s
Bit rate (RGB565, 16 bit/pixel) = 1.152M × 16 = 18.43 Mbit/s ≈ 2.3 MB/s

Check against DVP: even at a conservative 24 MHz PCLK, 8-bit DVP gives 24 MB/s raw capacity — over 10× the requirement. DVP is the right (cheaper, simpler) choice here: fewer SoC receiver requirements, easier debug on a Cortex-M with a parallel camera peripheral (e.g., a DCMI-style block), no PHY calibration needed.

Now suppose the same design instead targets 1080p30 RAW10 for a higher-end ISP/NPU pipeline: bit rate is 622 Mbit/s as computed above. A single DVP PCLK path would need 622 Mbit/s ÷ 8 bit = 77.75 MHz pixel clock on an 8-bit bus — well outside DVP's reliable single-ended range. CSI-2 with 2 lanes at ≥400 Mbps/lane (800 Mbps aggregate ≥ 622 Mbit/s) is the correct, and often the only, viable choice. This cross-check — comparing required bitrate against each interface's realistic ceiling — is the deciding calculation in any camera interface selection, not marketing datasheet peak numbers.

Practical Bring-Up Notes

• DVP timing: verify PCLK-to-data setup/hold against your MCU's capture peripheral sampling edge; a common bring-up bug is sampling on the wrong PCLK edge (rising vs. falling), producing a shifted/torn image.
• CSI-2 lane count vs. PHY speed trade-off: the same aggregate bandwidth can be reached with fewer lanes at higher per-lane speed or more lanes at lower speed — fewer lanes means fewer PCB pairs and lower routing complexity, but the PHY must support the higher per-lane rate.
• Lane/clock skew: CSI-2 D-PHY requires tight length-matching between differential pairs (typically <2–5 mm skew budget) and the clock lane; poor PCB layout causes intermittent frame corruption that's hard to distinguish from software bugs.
• Virtual channels: CSI-2 supports up to 4 virtual channels over one physical link, letting a single receiver multiplex several camera sensors or a sensor plus metadata stream — not possible on DVP without separate buses.
• Bridge chips: CSI-2-to-parallel (or vice versa) bridge ICs exist specifically because sensor and SoC ecosystems don't always match; factor bridge latency and format conversion into pipeline budget when used.

Key Takeaways

• DVP is a simple, single-ended, continuously clocked parallel bus — cheap and easy to bring up, but bandwidth-limited to roughly VGA/720p-class resolutions and frame rates.
• MIPI CSI-2 uses differential D-PHY (or C-PHY) lanes with packetized, data-type-tagged payloads, giving Gbps-class per-lane bandwidth needed for 1080p/4K and multi-camera systems.
• Bandwidth sizing is the deciding factor: compute pixel_rate × bits/pixel and compare against each interface's realistic (not peak-datasheet) throughput before committing to a design.
• CSI-2 costs complexity (PHY calibration, lane deskew, receiver IP) in exchange for pin efficiency, longer cable runs, and lower average power via LP/HS switching.
• Pin count and PCB routing favor CSI-2 for compact/flex-cable camera modules; DVP still wins for low-cost, low-resolution designs where an MCU's built-in parallel capture peripheral is "free."