PCB & Hardware Design
PCB layout, schematic capture, signal integrity, power integrity, EMC design, and DFM/DFT methodologies.
320 topics · 1 with articles
Intern Engineer· 80
- Alternative Component Cross-Reference and Risk Assessment
- Annular Ring: IPC-6012 Minimum Ring Requirement
- Approved Vendor List (AVL) and Lifecycle Management
- BOM (Bill of Materials) Creation: MPN, Manufacturer, Distributor
- Back-Drilling (Controlled Depth Drilling): Stub Removal
- Board Outline and Mechanical Keepout Zones
- Capacitor Derating: Voltage Coefficient of Ceramic Caps
- Capacitor Selection: Dielectric (X7R, C0G/NP0, Y5V), Voltage, ESR
- Component Obsolescence Monitoring and EOL Alert Strategy
- Component Symbol Creation: IEEE Standard Pin Styles
- Connector Mechanical and Electrical Rating Selection
- Controlled Impedance Stack-Up: Single-Ended 50 Ω, Diff 100 Ω
- Coplanar Waveguide (CPW): Ground Gaps on Same Layer
- Copper Balancing: Fill Patterns to Prevent CTE Warpage
- Copper Weight Selection: 0.5oz, 1oz, 2oz per Layer
- Crystal Oscillator: Load Capacitance, ESR, PPM Stability
- DFM Stack-Up Review with Fabrication House Feedback
- Datasheet Reading: Absolute Maximum Ratings, Recommended Op. Cond.
- Datasheet Reading: Timing Diagrams, Application Circuits
- Decoupling Capacitor Rule: 100 nF per Power Pin, Bulk Cap
- Design Rule Check (DRC) Setup and Interpretation
- Design for Cost (DFC): BOM Cost Optimization Techniques
- Dielectric Material: FR4 (standard), Rogers 4350B, Megtron 6, Isola
- Differential Pair Impedance: Edge-Coupled Microstrip / Stripline
- Dk (Dielectric Constant) and Df (Loss Tangent) vs. Frequency
- Dog-Bone Via: Standard BGA Fan-Out Technique
- ESD Protection Device Selection: TVS, PESD, Rail-to-Rail
- Embedded Component PCB: Capacitor Inside Laminate
- Engineering Change Order (ECO) Process and Traceability
- Ferrite Bead Selection: Impedance vs. Frequency Curve
- Ground Plane Continuity: No Gaps Under High-Speed Traces
- High-Frequency PCB: Rogers RO4003C Stack-Up for RF
- IPC-2221 Generic PCB Design Standard Overview
- IPC-2612: Schematic Documentation Standard
- Impedance Test Coupon: On-Panel Test for Fabrication Control
- Inductor Selection: DCR, SRF, Saturation Current, Q-Factor
- Layer Functions: Signal, Power Plane, Ground Plane, Mixed
- Layer Order for 4-Layer Board: Sig-GND-PWR-Sig
- Layer Order for 6-Layer Board: Sig-GND-Sig-Sig-PWR-Sig
- Level Shifter Selection: Unidirectional, Bidirectional, Auto-Dir
- MCU / SoC Selection: Core, Flash, RAM, Peripherals, Power
- MOSFET Selection for Load Switch: Vgs(th), Rds(on), Qg
- Microstrip Impedance Formula: Z0 vs. W, H, εr
- Min Trace Width and Spacing: IPC-2221 Current Capacity
- Mixed-Voltage System Design: 1.8V, 3.3V, 5V Interfaces
- Multi-Channel Schematic Design with Replication
- Net Class Definition: High-Speed, Power, Analog Classes
- Net Naming Convention: Signal Names, Power Rails, Labels
- Netlist Export and Import: Schematic-to-Layout Flow
- Optocoupler Selection: CTR, Bandwidth, Isolation Voltage
- PCB Fabrication Tolerances: Trace, Spacing, Hole Size
- PCB Layer Count Selection: 2L, 4L, 6L, 8L, 10L, 12L
- Panelization: V-Score, Tab-Route, Fiducial Placement
- Polarized Component Marking Convention (Diodes, Caps)
- Power Plane Cavity and Resonance Analysis
- Power Symbols: VCC, GND, PWR_FLAG Placement Rules
- Reference Designator Numbering Convention (R, C, U, J…)
- Resistor Selection: Tolerance, TCR, Power Rating, Size
- Rigid-Flex PCB Design: Flex Zone, Coverlay, Bend Radius
- Schematic Capture Tools: Altium Designer, KiCad, OrCAD
- Schematic Page Hierarchy: Top-Level and Sub-Sheets
- Schematic Review Checklist: ERC Pass and Peer Review
- Silkscreen Layer: Reference Designator, Polarity, Outline
- Solder Mask: LPI Color, Expansion Over Pads, Tented Vias
- Split Power Plane: Proper Routing of Signals Across Splits
- Stack-Up Symmetry: Preventing Board Warpage
- Stack-Up for HDI (High Density Interconnect): Staggered Micro-Via
- Stackup File Submission to Fabrication House
- Stripline Impedance Formula: Z0 for Embedded Traces
- Surface Finish: HASL, ENIG, OSP, ENEPIG Comparison
- System Block Diagram: Top-Down Architecture to Schematic
- Testpoint and Debug Header Placement Best Practices
- Thermal Via: Heat Conduction from Component to Inner Plane
- Variant Management: Assembly Variants in Altium
- Version Control for Schematics: Git with Altium/KiCad
- Via Aspect Ratio: IPC-2226 Reliable Plating Limit
- Via Stub Effect at High Frequency: Impedance Discontinuity
- Via Types: Through-Hole (TH), Blind, Buried, Micro-Via
- Via-in-Pad: Fill and Cap for BGA Escape Routing
- Voltage Regulator Selection: LDO vs. Buck for Efficiency
Junior Engineer· 40
- 3W Rule: Trace Separation = 3× Trace Width to Reduce Crosstalk
- AC Termination: Series RC to Eliminate DC Power
- CTLE (Continuous Time Linear Equalizer) in Receiver
- Channel Simulation: Ansys SIwave, Cadence Clarity, HyperLynx
- Characteristic Impedance: Z0 = √(L/C) for PCB Trace
- Crosstalk: Capacitive (Near-End NEXT, Far-End FEXT)
- DDR4 Address/Command Bus: Fly-By with Termination
- DDR4 Data Group: DQ/DQS Length Match within Group ±5 mil
- DDR4 Layout: Fly-By Topology, Daisy Chain, T-Branch
- DDR5 Inline ECC: Byte-Lane Architecture
- DFE (Decision Feedback Equalizer) in SerDes
- Differential Pair Routing: Keep Together, No Stubs
- End Termination: Parallel Resistor to VCC/2 at Receiver
- Eye Diagram: Eye Height, Eye Width, Eye Mask Test
- Frequency Domain Analysis: Insertion Loss, Return Loss
- Ground Plane Slot Effect on Return Current Detour
- HDMI 2.1 Routing: 100 Ω Differential, Shield Traces
- IBIS Model: I/O Buffer Simulation for SI Analysis
- Intra-Pair Skew vs. Inter-Pair Skew Management
- Jitter Types: Random (RJ), Deterministic (DJ), Total (TJ)
- LVDS: 100 Ω Differential, Low EMI Signaling
- MIPI DSI / CSI-2: 100 Ω Differential, Lane Length Match
- PCIe Gen3/Gen4/Gen5: Differential Pairs, AC Coupling Cap
- PCIe Via Optimization: Back-Drill, Low-Stub Via Design
- Post-Layout SI Simulation: Extracted Parasitics with SI Tool
- Pre-Layout SI Simulation: Topology Exploration with HyperLynx
- Reflection Coefficient: Γ = (ZL - Z0) / (ZL + Z0)
- Return Current Path: Current Flows on Ground Plane Under Trace
- S-Parameter Measurement with VNA for PCB Channel
- SerDes Channels: Transmitter Pre-Emphasis, Receiver Equalization
- Signal Integrity Fundamentals: Reflection, Crosstalk, Noise
- Source Termination: Series Resistor at Driver Output
- Thevenin Termination: Two Resistors for Differential
- Time Domain Reflectometry (TDR): Impedance Profile Test
- Trace Length Matching: Single-Ended ±25 mil, Differential ±5 mil
- Transmission Line Effect: Electrically Long Line > λ/10
- USB 2.0 Differential Routing: 90 Ω, Length Match
- USB 3.2 Gen2 SuperSpeed: 85 Ω, Via Stub Minimize
- USB4 / Thunderbolt 4: 100 Ω, AC Coupling, EQ
- Via Stitching: Guard Vias Around High-Speed Differential Pairs
Middle Engineer· 80
- Anechoic Chamber Measurement: Radiated Emission Test
- Anti-Resonance Peak: Between Bulk and Bypass Caps
- Battery Management: Charge Path, Protection FET Layout
- Buck Converter Layout: Minimize Switching Loop Area
- Buck Converter: Inductor and Output Cap Close to IC
- Buck Converter: Input Capacitor Close to FET Drain/Source
- Bulk Capacitor: Low-Frequency Decoupling (10–100 µF)
- Cable Shield Grounding: Pigtail vs. 360° Circumference Clamp
- Capacitor ESR and ESL: Impedance Profile vs. Frequency
- Capacitor Placement Rules: Closest to IC Power Pin
- Class B Radiated Emission Limits: 30–1000 MHz
- Common-Mode Choke: CM Impedance, DM Impedance Ratio
- Conducted EMI: Common-Mode (CM) and Differential-Mode (DM)
- Conducted Emission Limits: 150 kHz–30 MHz (EN 55032)
- Conductive Gasket: Beryllium Copper, Wire Mesh, Foam
- Crystal Layout: Keep Short Traces, Guard Vias, No Plane Cut
- Current Density in Copper Trace: IPC-2152 Ampacity Chart
- DDR Termination Power Rail (VDDQ/2): Stability Design
- Decoupling Strategy for SoC: Datasheet Recommended Cap Kit
- Differential Signaling for EMI Reduction: LVDS, RS-485
- Dynamic IR Drop: Transient Simulation for Power Spikes
- EFT/Burst Immunity: IEC 61000-4-4 Test Setup
- EMC Fundamentals: Source, Path, Receptor Model
- EMI Absorber Material: Carbon-Loaded Ferrite Sheet
- EMI Regulations: FCC Part 15, CE (EN 55032), VCCI
- ESD Immunity: IEC 61000-4-2, Contact and Air Discharge
- Embedded Capacitance Layer: High-Dk Material in Stack
- Faraday Cage Shielding: Enclosure Aperture < λ/20
- Ferrite Bead Application: High-Frequency Supply Decoupling
- Ferrite Clamp on Cable: Common-Mode Choking
- GaN and SiC Layout: Minimize Commutation Loop Inductance
- Ground Plane Continuity for Return Current Control
- Guard Ring / Guard Trace: Shielding Analog from Digital Noise
- High-Frequency Decoupling: 10 nF, 1 nF Close to IC
- High-Speed Clock Routing: Shield Traces on Both Sides
- IEC 60601-1-2: EMC for Medical Electrical Equipment
- IR Drop Analysis: Static Voltage Drop Map Across Plane
- Impedance Budget: IC VR Spec to Die Capacitance
- Isolation: Transformer and Optocoupler for CM Noise Break
- LDO Stability: Output Capacitor ESR Zero Requirement
- LISN (Line Impedance Stabilization Network): Conducted Test
- Low-Frequency Magnetic Field: IEC 61000-4-8
- MIL-STD-461: Military EMC Requirements (CE102, RE102)
- MOSFET Gate Drive Layout: Minimize Gate Drive Loop
- Metal Shield Can: Tin-Plated, Soldered or Snap-On
- Mid-Frequency Decoupling: 100 nF Ceramic at Power Pin
- Multi-Phase Buck: Interleaved Switching Noise Reduction
- Multi-Rail PDN: 1.0V Core, 1.8V I/O, 3.3V Analog Rails
- On-Die Capacitance: Part of PDN Hierarchy at High Freq.
- PCB Edge Stitching Vias: Reduce Edge Radiation
- PCB Slot Antenna: Avoid Gaps in Ground Plane
- PCB-Level Pre-Compliance Test: Near-Field Probe + Spectrum Analyzer
- PDN Impedance Target: Z_target = Vripple / I_transient
- PDN Simulation: Ansys SIwave, Cadence Voltus, Zuken
- Pi Filter (LC-C): Two-Stage EMI Attenuation
- Picotest Impedance Analyzer: PDN Measurement Technique
- Power Distribution Network (PDN) Concept and Goal
- Power Monitoring: Voltage and Current Sense Points
- Power Plane Inductance: Width, Length, and Return Path
- Power Plane Pour: Copper Fill, Thermal Relief Trade-off
- Power Plane Slotting: Separating Digital and Analog Domains
- Power Plane Void Fill: Copper Hatching vs. Solid Fill
- Power Sequencing: Enable Order and Ramp Rate Control
- Radiated EMI: Electric Field (E) and Magnetic Field (H)
- Radiated Immunity: IEC 61000-4-3 Field Strength Levels
- Resonance in PDN: Standing Wave Between Planes
- Return Current Path: EMI from Long Return Current Loops
- Seam and Gasket in Enclosure: EMC Gasket Selection
- Slot Antenna Effect: Power Plane Slot Under Trace
- Solid Copper Plane vs. Poured Ground Comparison
- Spread Spectrum Clocking (SSC): EMI Reduction Technique
- Surge Immunity: IEC 61000-4-5 Waveform and Level
- Switching Regulator EMI: Frequency, Harmonics, Spread-Spectrum
- Thermal Relief: Star vs. Direct Connect to Power Plane
- USB PD Sink: VBUS Decoupling and CC Logic Filtering
- VRM Output Impedance: Closed-Loop Bandwidth Impact
- Via Inductance in PDN Path: Low-Inductance Via Pair
- Voltage Regulator Placement: Close to Load, Short Path
- X-Capacitor: Differential-Mode Noise Suppression
- Y-Capacitor: Common-Mode Noise to Ground Path
Senior Engineer· 80
- ADC Ground: AGND and DGND Connected at ADC GND Pin Only
- ADC Input Layout: Anti-Aliasing Filter Close to ADC
- ADC Reference Decoupling: Low-Noise Cap on VREF Pin
- AOI (Automated Optical Inspection): Layer Setup and FOV
- Analog Filter PCB: Close Component Grouping, Short Paths
- Analog Ground Plane: Separate AGND and DGND
- Analog Power Rail Filtering: LC Filter Before Analog Section
- Analog Test Points: Easily Accessible for Scope Probing
- Assembly Drawing: Top and Bottom View, BOM Cross-Reference
- Audio Codec Layout: AGND Plane, Short Analog Paths
- BGA Pad Design: Non-Solder Mask Defined (NSMD) vs. SMD
- Bare Board Test (BBT): Open/Short Electrical Test
- Board Edge Clearance: 5mm from Components to Edge
- Capacitor Matching: Same Type, Adjacent Placement
- Charge Pump Noise: Switch Node Shield, Low-Noise Cap Filter
- Clean Room Requirements: PCB Handling and Storage
- Conformal Coating Specification: Thickness, Type, Masking
- Conformal Coating on Analog Boards: Masking ADC, Connectors
- Crystal Oscillator Layout: Short Traces, No Ground Plane Under
- Current Sense Resistor: Kelvin (4-Terminal) Footprint
- DAC Output Layout: Short Path to Load, Low-Impedance Drive
- DFM (Design for Manufacturability) Review Checklist
- DFT (Design for Testability): Test Access Planning
- Differential Analog Signal: Matched Traces, Low-Loop Area
- Double-Sided SMT: Bottom-Side Component Height Limit
- EMI into Analog: Bulk Ferrite at Power Entry, Guard Ring
- ESD Workstation Setup: Grounded Mat, Wrist Strap, Ionizer
- Fiducial Mark Design: 1mm Copper Circle, 3mm Clearance
- Fine-Pitch QFP Layout: 0.4mm and 0.5mm Pitch Land Pattern
- Flex Cable Connector: Impedance Continuity to Rigid PCB
- Flying Probe Test: Fixtureless, Slower, Lower Cost
- Functional Test Fixture: Pogo Pin Interface Design
- Ground Plane Split: Cut Line Under Analog-Digital Boundary
- Hall Effect Sensor Layout: No Magnetic Material Nearby
- High-Voltage Analog: Creepage and Clearance > IPC-2221
- ICT (In-Circuit Test): Bed-of-Nails Fixture Testpoint Grid
- IPC-7351 Land Pattern Generator: Courtyard, Pad, Silkscreen
- IPC-7711/7721: Rework Procedures Reference
- IPC-A-610 Assembly Acceptance: Class 1, 2, 3 Criteria
- ISO 9001 Quality Management Integration with PCB Process
- In-System Programming (ISP) Header: SWD, SPI, UART
- Instrumentation Amplifier Layout: Guard Trace Around Inputs
- Isolation Barrier: Digital Isolator Placement, Split Plane
- JTAG Boundary Scan: Header Connector Placement (TDI, TDO, TMS, TCK)
- Low-Noise Amplifier: Short Input Traces, Guard Ring
- MEMS Sensor Layout: No Stress-Inducing Via Under Die
- Minimum Hole Size: Mechanical Drill vs. Laser Drill
- Minimum Trace Width and Spacing per Fabrication Capability
- Mixed-Signal ICs: Internal Boundary Between Analog and Digital
- Multi-Turn Potentiometer PCB Mounting and Pad Design
- ODB++ and IPC-2581: Complete Manufacturing Data Package
- Op-Amp Layout: Minimize Stray Capacitance on Inverting Input
- Op-Amp Power Supply Decoupling: 10 µF + 100 nF at Each Rail
- PCB Depanelling: Router, V-Score, Laser Cut Method
- PLL VCO Layout: Low-Noise Supply, Shield from Digital
- Pad-to-Pad Spacing: Solder Bridge Risk Assessment
- Panel Breakaway Tab: Minimum 3 Tabs per PCB Edge
- Photodiode TIA Layout: Guard Ring, Minimize Capacitance
- Pick-and-Place File: Centroid (X, Y), Rotation, Side
- Potting and Encapsulation: Urethane, Epoxy Selection
- Precision Resistor Matching: Same Orientation, Common-Centroid
- REACH SVHC Declaration: Substance of Very High Concern
- RF Matching Network: Compact, Close to IC, Proper Ground
- RF Section Layout: 50 Ω Microstrip, No Vias in RF Path
- RTD / Pt100 Layout: 4-Wire Kelvin Connection Traces
- RoHS Compliance: Lead-Free Solder, Restricted Substances
- SMD Component Tombstoning Prevention: Balanced Pad Design
- SMT Assembly Direction: Component Orientation for Wave
- Sensor Interface Layout: Shield Trace, Guard Ring, Low Loop Area
- Star Ground Point: Single Connection AGND-DGND
- Stencil Design: Aperture Reduction for Fine-Pitch ICs
- THT Component Lead Length: Trim After Wave Solder
- Testpoint Design: 1mm Diameter, 2.54mm Grid Preferred
- Thermal Gradient Effect on Analog: Component Orientation
- Thermocouple Interface: Kelvin Connection, Isothermal Zone
- Transformer Orientation: Minimize Coupling to Nearby Traces
- Via-in-Pad: Filled and Capped Requirement for BGA
- WEEE Directive: End-of-Life Recycling Label
- Wheatstone Bridge Layout: Matched Temperature for All 4 Arms
- X-Ray BGA Inspection: Void Measurement, Short Detection
Distinguished Engineer· 40
- 3D PCB Model Export: STEP/IGES for Mechanical Clearance Check
- BERT (Bit Error Rate Test): High-Speed Serial Channel Test
- CE Marking: LVD and EMC Directive for PCB-Based Products
- Conducted Emission Test: LISN, EN 55032 Class B
- Drop Test: IEC 60068-2-27 Shock Profile
- EFT/Burst Test: IEC 61000-4-4 Level 4 (4 kV, 5/50 ns)
- ESD Test: IEC 61000-4-2 Level 4 (8 kV Contact, 15 kV Air)
- Eye Diagram Measurement: BER, Mask Margin Test
- FCC Part 15: Class B Certification for PCB-Level Products
- HALT (Highly Accelerated Life Test): Vibration + Thermal Stress
- HASS (Highly Accelerated Stress Screen): Production Screen
- Humidity Test: 85°C / 85% RH (Highly Accelerated Stress)
- IP Rating Test (IEC 60529): IP67, IP68 Immersion Test
- IPC-2221: Generic PCB Design Standard
- IPC-2226: HDI PCB Design Standard
- IPC-6012: Qualification and Performance of Rigid PCBs
- IPC-A-600: Acceptability of Printed Boards (Bare Board)
- ISO 9001: Quality Management for PCB Design and Production
- J-STD-001: Soldering Quality for Electronic Assemblies
- LVS (Layout vs. Schematic) Netlist Comparison
- Logic Analyzer: Protocol Decode (SPI, I2C, UART, CAN)
- Oscilloscope Measurement: Rise Time, Overshoot, Ringing
- PCB Design Rule Check (DRC): Clearance, Width, Drill Rules
- PCB Post-Production Audit: First Article Inspection (FAI)
- Power Integrity Simulation: PDN Impedance Profile
- Power Rail Probing: LCRZ Meter, Impedance vs. Frequency
- Pre-Compliance Scan: Near-Field Probe, Spectrum Analyzer
- Radiated Emission Test: Semi-Anechoic Chamber, OATS
- Radiated Immunity: IEC 61000-4-3 (10 V/m, 80–1000 MHz)
- RoHS 3 (EU 2015/863): Restricted Substance Compliance
- Schematic Peer Review: ERC Errors, Net Shorts, Floating Pins
- Signal Integrity Simulation: Pre- and Post-Layout SI Analysis
- Surge Test: IEC 61000-4-5 Level 4 (2 kV, 1.2/50 µs)
- TDR Measurement: Impedance Profile Along PCB Trace
- Thermal Camera Inspection: Hot Spot Localization on Board
- Thermal Shock: MIL-STD-810 Method 503, -55°C to +125°C
- Thermal Simulation: Junction Temperature, Hot Spot ID
- UL 94: PCB Base Material Flammability Rating (V-0, V-1)
- VNA Measurement: S11, S21 for RF Traces and Filters
- Vibration Test: Sinusoidal and Random per MIL-STD-810