First-Order System: Time Constant τ, DC Gain K

What is a first-order system and why does it matter in control design?

A first-order system is any plant, circuit, or sensor whose behavior is captured by a single energy-storage element — one capacitor, one inductor, one thermal mass — and whose transfer function reduces to G(s) = K/(τs + 1), where K is the DC gain and τ (tau) is the time constant in seconds. Every other dynamic feature of the system — rise time, bandwidth, phase lag — falls out of just these two numbers.

Definition and standard form G(s) = K/(τs + 1)

The standard form G(s) = K/(τs + 1) has a single pole at s = −1/τ and a DC value of G(0) = K. No zeros, no oscillation, no overshoot possible in the open-loop step response — the output moves monotonically from its initial value toward K times the input's final value. If you see a transfer function with a quadratic denominator, it's second-order and belongs to a different analysis (natural frequency ωₙ, damping ratio ζ); first-order systems never ring on their own.

Why first-order systems dominate embedded control problems

Most embedded control loops are first-order dynamics wrapped in a digital controller, because most physical actuation and sensing paths have exactly one dominant energy-storage element in the frequency range you care about. A brushed DC motor's electrical time constant is usually fast enough to ignore, leaving mechanical inertia and friction as a single first-order speed response. A thermal system's dominant mass dominates over secondary heat paths at the time scales a firmware loop runs at. Even when a real plant is technically second- or third-order, one pole is often 10x to 100x closer to the origin than the rest, and the far poles can be neglected for loop-shaping purposes — the system behaves as first-order for all practical bandwidth decisions.

Physical examples: RC circuits, motor speed, thermal systems

An RC low-pass filter, a motor's speed response to armature voltage, and a heated enclosure's temperature response to duty cycle all reduce to the same G(s) = K/(τs + 1) form, just with different physical meanings attached to K and τ: volts/volt or °C/duty-cycle for K, and RC seconds, J/b mechanical seconds, or thermal mass/conductance seconds for τ. Once you can read τ and K off a datasheet curve or a differential equation, you can predict the closed-loop behavior of an RC filter, a motor servo, or an oven controller using the same arithmetic.

How does DC gain K shape steady-state system behavior?

DC gain K is the ratio of steady-state output to steady-state input once all transients have died out — it answers "where does the system end up," not "how fast does it get there."

DC gain as the ratio of output to input at steady state

For a step input of amplitude A, the first-order system's output asymptotically approaches K·A as t → ∞. Set s = 0 in G(s) and you get G(0) = K directly; this is why K is called the "DC" gain, evaluated at zero frequency.

Calculating K from the transfer function numerator and pole

If G(s) is given in unnormalized form, say G(s) = b/(as + c), you get K by dividing both numerator and denominator by c: K = b/c, and τ = a/c. Always normalize to K/(τs+1) form before reading off either number — pulling K from the raw numerator without dividing by the pole coefficient is the single most common sign-and-scale error in this kind of analysis.

Impact of K on system accuracy and error magnitude

In open loop, K sets the output amplitude for a given input amplitude, so an undersized K means the plant never reaches its target. In closed loop with unity feedback, K of the open-loop (plant + controller) determines steady-state error directly: for a Type 0 system under a step reference, Ess = 1/(1+K). A plant with K = 9 driven by a pure proportional controller leaves 10% steady-state error no matter how long you wait. The full error-specification vocabulary — rise time, settling time, overshoot, and steady-state error together — is covered in Performance Specs: %OS, Ts, Tr, Tp, Ess.

Trade-off between high gain and stability margins

Pushing K up to shrink Ess is free in a pure first-order open loop, but it is never free once you close the loop with real sensors, ADC delay, and actuator saturation. Raising loop gain pushes the crossover frequency higher, eating into phase margin from any parasitic delay, and amplifies measurement noise that rides on the feedback signal — a subject covered at length in Noise Amplification: T(s) at High Frequency. The practical rule: pick the smallest K that meets the Ess spec, not the largest K you can get away with.

What does the time constant τ tell you about system speed?

τ is the time, in seconds, for a first-order system's step response to cover 63.2% of its total change — it is the single number that sets every speed-related spec of the system.

τ as the dominant time scale of the system

A step response y(t) = K·A·(1 − e^(−t/τ)) reaches 63.2% of its final value at t = τ, 86.5% at t = 2τ, 95.0% at t = 3τ, and 98.2% at t = 4τ. There's no overshoot and no ringing to characterize — τ alone is the entire speed story.

Relationship between τ and the pole location s = −1/τ

The transfer function's pole sits at s = −1/τ on the real axis. A pole further left (more negative, meaning τ is smaller) corresponds to a faster-decaying transient; a pole near the origin (large τ) decays slowly. This is why pole location s = −1/τ is the standard shorthand control engineers use for both speed and, in closed-loop contexts, stability margin — a pole crossing from the left half-plane to the right half-plane (τ going negative) means the system diverges instead of settling.

How τ determines rise time and settling behavior

Rise time (10%–90%) for a first-order step response is approximately Tr ≈ 2.2τ, and settling time to within 2% of final value is approximately Ts ≈ 4τ. These are the same Tr and Ts terms used in performance-spec work, and for a pure first-order system they collapse to closed-form multiples of τ rather than needing ζ and ωₙ.

Bandwidth and τ: the inverse relationship ω_bw ≈ 1/τ

The −3 dB bandwidth of a first-order system is ω_bw = 1/τ rad/s. Halving τ doubles bandwidth; there is no way to get a faster system without either reducing τ physically (smaller RC, lower inertia, less thermal mass) or wrapping the plant in feedback that reshapes the effective pole.

How do you extract τ and K from a real circuit or plant model?

You extract τ and K by writing the governing differential equation, Laplace-transforming it, and normalizing the result so the denominator's constant term is 1.

Deriving G(s) from differential equations

A general first-order ODE has the form a·dy/dt + c·y = b·u(t). Taking the Laplace transform with zero initial conditions gives (as + c)Y(s) = bU(s), so G(s) = Y(s)/U(s) = b/(as + c). Dividing numerator and denominator by c yields G(s) = (b/c) / ((a/c)s + 1), which is exactly K/(τs+1) with K = b/c and τ = a/c.

Reading τ and K directly from normalized transfer function form

Once a transfer function is written as K/(τs + 1), both numbers are literally sitting in the expression — no further algebra needed. This is why normalization is worth doing even when it feels like busywork: every downstream calculation (Ess, Tr, Ts, ω_bw) assumes this form.

Circuit example: RC low-pass filter pole and gain

For a series R–C low-pass filter with output taken across the capacitor, the governing equation is RC·dVout/dt + Vout = Vin. Here a = RC, c = 1, b = 1, so τ = RC seconds and K = 1 V/V. For R = 10 kΩ and C = 100 nF, τ = 10×10³ × 100×10⁻⁹ = 1.0 ms, giving a −3 dB bandwidth of 1/τ ≈ 1000 rad/s (≈159 Hz) and unity DC gain — the filter passes low-frequency signals through unchanged and only attenuates above that corner.

Identifying τ and K from measured step response data

With no schematic in hand, apply a known step input and record the output on a scope or via the microcontroller's ADC. K is the ratio of final steady-state output to input amplitude. τ is the time at which the output has risen to 63.2% of its total step change — or, more robustly against noise, fit ln(y_final − y(t)) versus t and read τ as the negative reciprocal of the line's slope. A single clean step response is enough to identify both parameters of a true first-order plant.

How does first-order dynamics affect closed-loop control performance?

Closed-loop performance of a first-order plant is bounded by the same τ and K that describe it open-loop, modified by whatever gain and compensation the controller adds around it.

Effect of τ on achievable bandwidth and response speed

Wrapping a first-order plant in proportional feedback with gain Kp produces a new closed-loop pole at −(1+Kp·K)/τ, which is always faster than the open-loop pole — proportional gain trades steady-state accuracy improvements for genuine bandwidth increases on a first-order plant, unlike on higher-order systems where excessive gain induces oscillation.

How K determines steady-state error for unity feedback

For unity feedback with open-loop transfer function Kp·K/(τs+1), the closed-loop DC gain is Kp·K/(1+Kp·K), always less than 1, meaning some steady-state error always remains under pure proportional control of a Type 0 plant. Driving Ess to exactly zero needs integral action, discussed below.

Pole location s = −1/τ and its role in stability

A first-order system alone cannot go unstable in the classic oscillatory sense — its single real pole either sits in the left half-plane (stable, decaying) or, in pathological cases like a thermal runaway or positive-feedback circuit, crosses into the right half-plane (unstable, diverging). The sign of τ itself, not just its magnitude, is the stability test: positive τ decays, negative τ grows without bound.

Trade-off: fast τ improves speed but reduces noise immunity

A smaller τ means a wider bandwidth, and wider bandwidth means more sensor noise and quantization noise from the ADC gets through to the control signal and, via the loop, to the plant output — the same high-frequency noise-gain problem analyzed in Noise Amplification: T(s) at High Frequency. Picking τ (or the closed-loop bandwidth, when it's a design choice) is as much about rejecting noise as it is about chasing speed.

What are common design patterns for first-order systems?

Real first-order control loops are built from a small set of recurring patterns, each trading speed, accuracy, and robustness differently.

Proportional control: setting loop gain to meet error specs

Pick Kp from the Ess requirement — Ess = 1/(1+Kp·K) — then verify the resulting closed-loop τ_cl = τ/(1+Kp·K) still meets the rise-time spec and doesn't demand a bandwidth beyond what your sample rate or actuator can support (a rule of thumb: sample rate should be at least 10x the closed-loop bandwidth).

Integral action and the pole-zero cancellation concept

Adding an integrator (PI control instead of pure P) drives Ess to zero for a step reference regardless of plant K, because integral action adds a pole at the origin and infinite DC gain to the open loop. A common compensator design pattern places the PI zero at the plant's pole location (zero at s = −1/τ) to cancel it exactly, leaving a simple integrator response in closed loop — clean in theory, but sensitive to any mismatch between the assumed τ and the real one, since imperfect cancellation leaves a slow residual pole.

Lead compensation to increase bandwidth without sacrificing τ

When the plant's native τ is too slow and proportional gain alone runs out of headroom before meeting a rise-time spec, lead compensation adds a zero before the pole in the compensator's own transfer function, boosting phase margin and allowing higher crossover frequency without the gain margin loss that plain proportional gain would cause.

Sensor and actuator first-order lags in the control path

Thermocouples, filtered ADC front ends, and motor drive electronics each add their own first-order lag in series with the plant, and these extra τ's stack: an outer loop designed assuming only the plant's τ will have less phase margin than predicted once the sensor's lag is included. Always check whether the sensor or actuator time constant is within 5x to 10x of the plant's τ — if it is, it is not negligible and must be folded into the loop-gain analysis, often as an additional pole that turns your clean first-order design into an effective second-order one.

Related reading

• First-Order Step Response: Rise Time, Settling Time — checking rise and settling times.